International Journal of Reconfigurable Computing / 2019 / Article / Tab 9

Research Article

SIFO: Secure Computational Infrastructure Using FPGA Overlays

Table 9

Influence of number of gates.

Gate numbersTimeSpeedup compared with SWSpeedup improvement

5 XOR 5 AND186778.20
10 XOR 10 AND1488810.291.25
15 XOR 15 AND1225212.501.22

64-bit multiplication problem; 300 MHz main clock and 200 MHz local clock.

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