Automatic Pipelining and Vectorization of Scientific Code for FPGAs

<div>Resource usage for various OpenCL-HDL hybrid vectorized versions, normalized against resource usage for nonvectorized OpenCL baseline, for the second example (simulating the Coriolis force).</div>

International Journal of Reconfigurable Computing

fig13

Figure 13

Figure 13: Automatic Pipelining and Vectorization of Scientific Code for FPGAs 