High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

Table 2

Relative performance of the back-end decision circuit.

Reference	Technology; (CMOS, nm)	Bias supply; (V)	Power; (mW)	Maximum speed/power (GHz/W)	Capacity/sampling freq.	Core area; (mm^2)	FOM2 (from (23))
This work	90	1.2	7.536	265.39	0.1~2.0 Gbps	0.125	0.2212
[39]	130	1.8	180	8.9	1.6 GS/s	0.42	0.0049
[40]	65	1.2	110	9.1	1.0 GS/s	0.87	0.0076
[41]	65	1.2	60	16.7	1.0 GS/s	0.2	0.0139
[42]	65	1.0	40	55	2.2 GS/s	0.3	0.055
[43]	90	1.3	92	11.96	1.1 GS/s	0.37	0.0092
[44]	45	1.1	50	50	2.5 GS/s	1	0.0455
[45]	65	1.0	35	42.86	1.5 GS/s	0.5	0.0429
[46]	65	1.2	6.7	149.25	1.0 GS/s	0.11	0.1244
[47]	180	1.8	2.52	396.82	1.0 GS/s	—	0.2205
[48]	130	1.2	120	26.67	3.2 GS/s	0.18	0.0222
[49]	90	1.4	180	23.33	4.2 GS/s	0.66	0.0167