International Scholarly Research Notices

International Scholarly Research Notices / 2012 / Article

Research Article | Open Access

Volume 2012 |Article ID 435209 |

Apratim Roy, "High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver", International Scholarly Research Notices, vol. 2012, Article ID 435209, 15 pages, 2012.

High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

Academic Editor: S. Gift
Received07 Sep 2012
Accepted24 Sep 2012
Published14 Nov 2012


A new microwave receiver configuration which transmits reference pulses embedded in data streams for synchronization is analyzed with a 90-nm IBM CMOS standard. A two-stage cascode low-noise amplifier (LNA) is proposed for the receiver front-end which is matched by a passive network to save on power-expensive matching techniques. The amplifier exploits a double-differential topology and achieves a below 4 dB noise figure near the center frequency. The overall 3-dB bandwidth is 3.3 GHz with peaking up to 20.5 dB in the -band. The back-end of the receiver is implemented through an adjustable analog window-detection circuit. It avoids the use of control voltage generators and sample-hold (S/H) blocks to save electronic overhead and is simulated with a 0.1~2.0 Gbps pulse stream. The achieved speed-to-power ratio for the back-end has a maximum limit of 266 GHz/W. When compared against simulated results of published literature, the proposed designs show improved performance in terms of small-signal gain, noise, speed, and power dissipation.

1. Introduction

The ultrawideband technology, with benefits like high data rate, low cost, and low complexity, has been considered as a promising initiative for short-distance wireless applications [1]. The main challenge of designing a wideband transceiver involves satisfying linearity, reverse isolation, gain, and noise requirements over a wide bandwidth. Different circuit techniques have been proposed in recent literature to achieve wideband operation for a radio-frequency (RF) front-end [2, 3]. Focus on the design of the back-end section of the receiver, on the other hand, has received relatively less attention. The wide variety of modulation and multiplexing techniques employed by the ultrawideband (UWB) system allow it to achieve high bit rates over a wide frequency range. For example, recent developments in UWB standards have proposed to exploit OFDM (orthogonal frequency division multiplexing), IR (impulse radio), and TR (transmit-reference) modulation techniques. Among them, IR-UWB is suitable for low rate applications (e.g., sensor network) and OFDM-UWB is more appropriate for high data rate transmission [4].

The idea of a transmit-reference (TR) system is that by injecting a reference pulse over the same channel as the information signal estimation of the channel model (to be directly used for convolution by a mixer) can be avoided. It is recognized that a TR system may face some limitations for a band-limited channel, but it allows data symbols to be decoded without direct calculation of multipath channel coefficients [5]. To realize this standard, efficient implementation is necessary for a millimeter-wave front-end low-noise amplifier (LNA) which immediately follows the receiving antenna and an RF multiplier (mixer) which correlates the received pulses with their delayed version [6]. As design requirements, this low-noise amplifier needs to provide reduced power consumption, low reflection (return) losses at peripheral ports, and reasonable forward gain. We aim to incorporate a double-differential topology for the LNA to provide less sensitivity to bias supply or common-mode noise, improved power supply rejection ratio, and a more linear behavior [7]. To complete the back-end section of the TR-receiver, a window comparator subcircuit with a current limiting mechanism is proposed which determines the final speed to power ratio at the receiver load-port. It avoids auxiliary electronic overheads in the form of control voltage generator and sample-hold blocks, therefore improving the overall performance of the transceiver.

To initiate the design of the receiver front-end, a high-gain two-stage cascode amplifier using a differential configuration is presented on an IBM .09-μm CMOS platform. The LNA operates in the -frequency band with a 3.3 GHz bandwidth. Noise figure stays around 3.5 dB near the center point and the circuit is expected to be unconditionally stable according to Rollett criterion. Passive matching techniques are used at the interfacing ports to avoid area consuming transmission line matching. The amplifier is followed with a 90 nm threshold detection block using a separate control circuit to manipulate the ratio of integrated current mirrors. Its speed to power ratio ranges from 14 to 266 GHz/W as the input capacity is raised from 0.1 to 2.0 Gbps. The decision circuit dissipates only 7.5 mW of power (including bias circuits) and completes the implementation of the back-end part of a TR-receiver.

The paper is organized as follows. Section 2 introduces the proposed front- and back-end architectures of a TR-receiver. The operation of the microwave amplifier circuit and the design of the window comparator are discussed in detail in Sections 3 and 4, respectively. The results from the front-end amplifier and the decision circuit in the back-end occupy the focus in Section 5. Finally, Section 6 summarizes the performance of the designs and compares them with simulated examples from published literature.

2. Proposed TR Front- and Back-End Architectures

The microwave front-end including the feature of self-synchronization and the back-end with a decision block are presented in Figure 1(a) in the form of a traditional TR-receiver. For this architecture, a simplified transmitted TR frame typically consists of a “data pulse” modulated by signal message and a “reference pulse” necessary for synchronization. The two pulses are separated by a temporal displacement (delay) predefined during the design of the transceiver. This TR-receiver does not depend on direct estimation of the interchip channel and requires an architecture with a lower power demand. For Figure 1(a), demodulation is executed without obtaining channel state information and the scheme is resistant to distortion due to multipath propagation [6]. The transmitted signal passes through the channel for wireless interconnection and is received by the collecting antenna which relays it to a microwave front-end low-noise amplifier (LNA). The amplifier boosts the degraded signal while limiting the thermal noise accumulated in the front-end. The amplifier output (RF signal) and its delayed version (LO signal), produced by a specially designed delay unit (DU), are subjected as excitations to an RF mixer or correlator. This feature of self-synchronization reduces the receiver's architectural complexity but introduces the challenge of designing analog delay lines to align the LO signal with the amplifier output [8]. At the end of the front-end, the RF mixer facilitates the process of decoding the input data form the pulse stream. So, it is evident that the microwave LNA is a critical component for the receiver front-end of a TR scheme. It is also observed that a majority of RF LNAs reported in literature have been implemented with single-ended configurations [911].

The proof of the operation of the TR transceiver has been reported in detail in literature [1216]. According to the model presented in [12], the signal of a TR scheme is grouped in individual message blocks. The length of each block is where the number of “data pulses” and “reference pulses” are denoted by and , respectively. If is the frame period of the standard, is a gaussian white noise function, is the received pulse function, and stands for the message stream, the received signal collected by the antenna in a TR scheme can be modeled with Here the noise function has a spectral density of and is calculated using the channel impulse response and the transmitted pulse function. If is the delay suffered by a cluster , is the delay of multipath relative to the arrival of cluster , and is the multipath gain factor, the channel impulse response in this case can be modeled with (in the absence of log-normal shadowing) [17] where and are the numbers of clusters and multipath for the distribution of clusters and signals. Here, the frame period has to be larger than the temporal spread introduced by the channel and the channel is assumed to be stationary according to the block fading assumption. At the end of the front-end, each data pulse is correlated with a template generated by the delay unit and the signal is passed to the back-end. A traditional approach to build the back-end section following the RF mixer would include the use of filters, a sample-and-hold block (S/H), and a separate decision circuit for threshold detection. This would necessitate the inclusion of control voltage generators for providing regulatory signals for integrator and sample-hold (S/H) sections. A separate circuit will also be needed to provide a calibrated reference voltage for driving the output decision circuit. If the output of the RF mixer does not have sufficient strength to drive the threshold detection section, further processing will be required before feeding the signal to the back-end. The aim of this paper is to propose an architecture which exploits a differential front-end and simplifies the circuit overhead of the receiver by implementing its back-end as an integrated comparator block.

Figure 1(b) shows the diagram of the proposed architecture for a transmit-reference receiver which employs a modified back-end section after the RF mixer. The front-end in this design is realized with a two-stage differential low-noise amplifier (LNA) with passive matching circuits. It makes the front-end compatible with differential topologies of the following RF mixer and improves the overall noise sensitivity of the receiver. The differential amplifier can also support direct connection to a double-balanced correlator and offers benefits like common-mode noise rejection with respect to substrate and power rail. Additionally, it has been reported that the differential architecture can influence the reduction of the second intermodulation product (IP2) [18]. On the other hand, the proposed back-end uses a window comparator and reduces the receiver's electronic burden by substituting S/H blocks with logic and buffer sections. The comparator is built with a transconductance amplifier core with integrated bias circuits to deliver the comparator reference voltage and the gate voltage for a tail current source. It also includes a multiplication factor control block to regulate the width of the detection window and a logic section which delivers the output signal of the window comparator. The buffer block at the output of the back-end is implemented with a pair of cascaded inverters. The proposed TR-receiver front- and back-end circuits are discussed in detail in the next section.

3. Matched Front-End Low-Noise Amplifier

The proposed double-stage high-gain low-noise amplifier, which immediately follows the antenna in the receiver front-end (see Figure 1(b)), is presented in Figure 2. The circuit uses two back-to-back connected fully differential amplifier stages which allow it to exploit the advantages of the differential topology for a multistage amplifier. It employs a passive reactive Y-shaped matching circuit to provide it with input (), interstage, and load port matching. With the inclusion of these matching circuits, the amplifier achieves very low reflection losses (minimum return loss is better than −18 dB at the interfacing ports.) Matching also contributes to the improvement of the amplifier's noise figure following a mechanism described in [19]. The fully symmetric structure is expected to make the architecture more resilient against process variation for the 90 nm technology. Using an LC tuning circuit as the resonance bank provides the amplifier with the ability to fine tune its center frequency. The inclusion of multiple integrated bias circuits leads the LNA to be driven by a single supply voltage (1.2-V). It manages a high small signal forward gain with the double-stage core and careful selection of bias currents provides it with simultaneous power and noise matching. The architecture will be compatible with a fully differential TR front-end where the RF mixer can be built with a double-balanced topology. The amplifier includes features like improved linearity (because of cancelation of intermodulation products), is more resistant to power supply noise, and supports the use of image rejection schemes, dipole antenna, and Gilbert mixers.

To maintain design symmetry for the first block of the design, with (60 μ/0.1 μ) play the role of driving transistors and with (50 μ/0.1 μ) insulate the second stage from the driving input. The central operating point of the front-end built with this cascode configuration is determined by and in the first block, which form a pair of resonance tanks in conjunction with associated capacitances. The resistive elements in the tanks ( and ) do not represent independently inserted components but model for parasitic contributions from adjoining tuning inductors. To include a provision of fine tuning, parallel capacitors are also included in the tanks in the form and . A source degenerating port matching network (built with and ) adjusts the input impedance offered by while works as a coupling capacitor. An LC matching branch is also placed at the input port of . To ensure a smooth transition of signal and to save on power penalty and noise contribution, a secondary passive linking network joins the intermediate nodes between the two stages. It is made with , , and for the left-half segment of the amplifier. , , and provide a similar service for the second set of intermediate differential nodes located on the right-half of the design. The linking circuits ensure that additional input matching networks are not necessary for the second stage of the differential amplifier, leading to a boost in the overall amplifier gain. The two cascode trees in the second stage are made with (50 μ/0.1 μ and 40 μ/0.1 μ) and (similar dimensions). They closely follow the size of the devices in the first block except for process variation. The reactive elements in the secondary resonating banks (, , and ) are carefully matched with their counterparts in the first stage to maintain a stable operating point. Finally, T-shaped passive matching circuits (previously placed with intermediate nodes) are also utilized for the differential load ports ( and ) to interface them with typical microwave loads that may follow. The components in the load matching circuits are designated as , , , and like. A tail transistor () is added with the bottom rail of the first stage to exert control over the overall bias current which is split between the differential half circuits. The tail current controlling arrangement is not repeated for the second block for easier manipulation of the bias current. The gate bias supply for the control device () and the gate signals for the driving transistors ( and ) necessitate inclusion of three bias circuits to push the concerned transistors in a region of saturation. This three-way supply rail is also included in Figure 2, built with diode-connected devices (2 μ/1 μ), (2 μ/1 μ), (4.7 μ/1 μ), and bootstrapping resistors (). For a 1.2-V 90-nm process, , , and are set to 0.851, 0.851, and 0.699 V, respectively. An interfacing balun (balanced-unbalanced) circuit is placed at the ports during simulation to interface the front-end with the antenna that feeds it. Three ideal coils () in a transformer formation facilitate this balanced to unbalanced conversion with coupling parameters . If we define a quality factor for the input network [20] appended with (excluding coupling capacitors), it will be a function of source impedance () and operating frequency () while relating to the gate-source capacitance () of the transistor : This quality factor has to be optimized to balance gain and bandwidth achieved by the first stage of the amplifier. In the resonance tank formed on top of , the quality factor of the reactive element () will ultimately determine the inductor's series resistance () which can be approximated by Therefore, this undesirable resistive element can be minimized by selecting a reasonable value for the drain inductor. The designer also has to be careful about large quality factors achieved at microwave frequencies, which can push up the resistive value of [21]. For the 90-nm CMOS process (with the presence of parasitic junction capacitors) the output resistance offered by the cascode device () has low to moderate values like The effective output resistance () seen from the load port of the first stage amplifier can be estimated using the adjoining resistive components with The quality factor seen by a load connected to the first stage can, therefore, be simplified as Tuning of the controlling parameters of this quality factor would influence the overall gain achieved by the first block of the double-differential amplifier. A very small would increase and, as a consequence, message bandwidth and gain of the LNA may suffer [20]. To set the operating point in the -band, the bank inductor () resonates with and an output capacitive element which can be calculated with where is the cascode capacitance seen from the drain of , represents extraneous parasitic elements existing between that node and ground, is the capacitance offered by a following stage (load), and stands for the output coupling capacitance. So, all these considerations have to be taken into account during the design of the low-noise amplifier. After careful selection of the reactive elements for gain-bandwidth optimization, the input impedance of the amplifier [7] looking from the gate terminal of the transistor can be derived as where is the transconductance of the transistor . The dimensions of , , , and the aspect ratio of are manipulated to eliminate the imaginary part of the expression (as part of input matching) which reduces the equation and matches it with characteristic source or antenna resistance (),

For the output matching circuit located on the left segment of the amplifier [22] (see Figure 2), the impedance can be derived as where , , and represent measures of reactance and is offered by the circuit block which follows the low-noise amplifier in the receiver. Now the expression can be reduced to if the parameters are manipulated to equalize , and . The design equation which makes equal to the first-stage output resistance () will be where is the real element of the port impedance . As an example, when and near the center frequency for the proposed design, if we set  Ω, then following (13) should result in being equal to and being matched with (see Figure 2). A similar matching mechanism is also executed through a reactive network connected with the node which is made with , , and .

Noise figure contributed by the driving transistors ( and for the first stage) of a differential amplifier has been modeled in literature [23] and is expressed in terms of quality factor of the input network , transit point (), and center frequency (): where is defined by zero-bias drain-conductance and device trans-conductance, correlates drain and gate noise functions, models channel noise, and models noise induced at gate terminal. If it is possible to partially cancel out the third and fourth components in (14), the expression for minimum noise figure (applicable for FET amplifiers) can be approximated by If the effect of the cascode device in the first stage () is considered, the cascode noise-factor () will be proportional to device transconductance () [24] where denotes the parasitic capacitance linking the two stages of the amplifier. Finally, an output balun block will be necessary to interface the amplifier if the following mixer or another front-end component is single-ended. The three reactive elements for the RFout port balun are denoted by , supported with carefully selected linking parameters (). In this arrangement, the bias supply is set to 1.2 V for process requirements.

4. Back-End Architecture

The proposed decision section for a TR-receiver back-end is driven by a window detector with output logic and buffer gates, thus relaxing the overhead requirements for the receiver design. The symmetric nature of the decision circuit makes it resilient with respect to variation of process. The controlling voltage of the tail current source in the design and the reference voltage of the comparator are provided with integrated diode connected bias circuits. The inclusion of multiple bias arrangements allows the back-end to be driven by a single supply rail (1.2-V) which eliminates the need for external gate supply voltages. Optimization of the bias currents for the comparator reduces their power requirement with respect to comparable analog detection circuits. The architecture of the receiver back-end is simplified by avoiding sample-hold blocks and using logic sections and buffer gates. This reduces the electronic burden on the comparator's transconductance amplifier core and pushes down its power demand even further. The window of detection for the decision circuit can be controlled by multiple design parameters, one of which is influenced by a multiplication factor control block with external switching signals.

Analog window comparators have primary applications in testing of controlled systems and they typically capture multiple analog inputs to produce the output in a decoded format. They are called window detectors because they respond when the difference between the two excitations of the decision circuit is within the range of [], with being the detection threshold for the comparator [25]. The proposed decision section, shown as a functional block diagram in Figure 3(a), is built on a differential input core, a number of current mirrors and a tail current source (the window decision circuit in Figure 3(b)), a mirror factor controlling block (Figure 3(c)), two bias supplies (Figure 3(d)), and an output logic section (Figure 3(e)). Transistors and (20 μ/0.1 μ) constitute the input differential pair where represents the input signal (driving excitation) coming from an RF multiplier in the TR-receiver and denotes a calibrated reference voltage for the decision circuit. So, the input network of the window comparator resembles a differential transconductance amplifier core. If the input voltage () falls in the vicinity of the threshold level (i.e., it is within the range ), the logic section implemented by transistors , (20 μ/0.1 μ), and , (40 μ/0.1 μ) produces a positive response in terms of output voltage. As a result, the comparator is able to detect whether the input signal falls within a particular window around the reference voltage or not [26]. If the tail bias current flowing through the design is , when both comparator excitations are sufficiently at the same level ( equals or resides within the range ), transistors , , , , and (20 μ/0.1 μ) remain in a region of saturation. A split current (/2) flows through the transistors which depends on the dimensions of current mirrors. The tail current source is implemented by a device (, 20 μ/0.1 μ) attached to the bottom power rail and powered by a gate bias supply. The two bias circuits in the design (see Figure 3(c)) are developed by diode connected transistors (, 0.1 μ/1 μ and , 5.45 μ/1 μ) which deliver calibrated dc voltages for and for . represent low to moderate values of impedance which ensure that remains at a value near the bias rail () and the reference level () can be fine tuned within the 0.6–1.2 V range using device dimensions (1–10 μm as width of ). Four p-type current mirrors are implemented by transistors , all following a unity mirror factor. The n-type current mirrors introduce a regulating mirror factor () as a way of controlling the width of the detection window. The first -type mirror is formed by (20 μ/0.1 μ) and (variable dimensions) which split the bottom current path in five ways so that can be adjusted by the designer. Inclusion of switching signals () for the devices turns it into a programmable current mirror which can be controlled by an external driving circuit. A similar extended mirror circuit is realized by the devices and , also driven by a 5-bit input signal. The factor can be compounded (raised above 5) by adjusting the dimensions of the control transistors () as multipliers of the width of . When the input voltage and the reference level are not in close proximity, currents flowing through devices and become and or vice versa with depending on the difference between the two inputs. The expression for the detection window width of the comparator ultimately takes the form of [25]: where is the carrier mobility, is the tail current, denotes the gate capacitance per unit area, is the current mirror factor, and indicates the aspect ratio of or . Because of the resemblance of the input pair of the comparator section with a differential transconductance () amplifier, its gain-bandwidth product () will depend on the input pair's effective load capacitance () where is a constant depending on load capacitance and is the overdrive voltage defined by Here and are the input signal and the threshold voltage for the input differential pair, respectively. The factor for the decision circuit is optimized to fine tune the detection window. The bias rail () may be connected with at least two of the switching combinations () to maintain a nominal value for (=2). Here, it is assumed that the relation between the output current and the input voltage of the two input transistors follows the standard equations of saturation region.

As indicated by the threshold expression, the detection window can be adjusted by changing the bias current which, in turn, is controlled by the voltage and the transistor . As carrier mobility and gate capacitance are intrinsic device parameters, the other controlling factors of the error threshold are the multiplying factor of the tail current mirrors () and the size of the input differential pair . The gate biasing voltages in the comparator are provided by biasing arrangements already discussed in relation to Figure 3(d) where voltages are collected from the drain terminals of . To evaluate the performance of the back-end, characterization of the window detector [26] is performed in detail in the next section and the responses from the decision block for TR inputs are discussed.

5. Results and Discussion

5.1. Front-End LNA

The proposed design is analyzed on an RF simulator including layout parasites generated by the 90-nm circuit elements to enable accurate prediction of microwave parameters during an RF analysis. In the first phase, the design parameters of the wideband low-noise amplifier are obtained on the 0.09-μm CMOS platform to evaluate power efficiency and gain performance of the proposed front-end.

5.1.1. Noise Performance

The projected noise figure () and theoretical noise figure contributed by the front-end amplifier are documented to be around 3.5 and 2.93 dB, respectively, near the center frequency of the message bandwidth, as shown in Figure 4(a). In total, the driving transistors (, in the front stage, , in the second block) are responsible for about 23% of the total accumulated noise and the percentage contribution is slightly lower for the insulating devices.

5.1.2. Propensity of Oscillation

The low-noise amplifier is expected to be unconditionally stable within the bandwidth as the Rollette stability factor (), plotted versus frequency in Figure 4(a), is always greater than 23 within the bandwidth, hence satisfying the criteria for nonoscillatory behavior [7]. This factor is defined in terms of -parameters: Therefore, the LNA is not prone to oscillating in the presence of unwanted noise or interference.

5.1.3. Power and No-Load Gains

Available gain (), transducer gain () and average power gain () coincide around the center frequency at 20.5 dB in Figure 4(b). This coincidence can be attributed to the matching networks included in the design. Available gain is an estimation of the power gain provided by the core amplifier without any matching, which is then lowered down to transducer gain after the addition of passive linking networks at intermediate and interfacing ports of the front-end. The no-load voltage gain of the amplifier reaches a higher limit with its peak touching 28 dB, as shown in the same figure.

5.1.4. and Stability Factor

Figure 5(a) shows the maximum small-signal forward gain () with a peak of 20.5 dB at the central operating point, managing a 3.3 GHz three-decibel bandwidth. To verify a second criterion for stability, the stability factor is also calculated for the amplifier and it resides within a range denoted by the inequality 0.3 1. The standard definition of the secondary factor () is given with

5.1.5. Input/Output Return Loss

Figure 5(b) verifies that the parameter representing reverse isolation () is always better than −55 dB within the bandwidth. As a measure of return losses incurred at the front-end ports, the same frame plots the input and output reflecting parameters ( & ) showing dips at −18 dB and −25 dB, respectively, and maintaining a separation of 30 dB with the peak of the amplifier's reverse isolation.

5.1.6. Region of Linear Behavior

The input referred 1-dB compression point (1 dB-) is crossed by the LNA at −15 d of input power which pushes the amplifier into a region of nonlinearity (see Figure 6). The 3rd order intersecting point for intermodulation products () settles near −4 d with respect to input power (theoretically, it should have a difference of 10 dB with 1 dB-). At this cross point, the front-end would deliver 10 d power to a matched load connected with the output port.

5.2. Window Detector in the Back-End

The results from the decision section (window detector with buffer gates, as discussed in Section 4) implementing the back-end of the TR-receiver are also obtained with 90-nm process parameters on a CMOS platform.

5.2.1. Dynamic Response

In an effort to study the dynamic behavior of the proposed back-end, the input at the reference port of the comparator block is tied with a zero-phase sinusoid and the signal port () is exited with a pulse of variable phase (0~360 degrees). The corresponding response in Figure 7(a) detects a driving signal positively (high) only when the two phases follow each other. With an increase in phase difference, the circuit response starts to resemble nonuniform pulse peaks.

5.2.2. Behavior for Variable Amplitude

Both input ports of the detection subcircuit are tested with a number of combinations of frequency and magnitude for the input sinusoids. With a fixed reference level (settled at 1000 mV), the signal port is tied to a sinusoid whose amplitude is raised in steps from 500 to 2500 mV. Figure 7(b) demonstrates that, with an increase in the difference of magnitude between the two excitations or for signals existing outside the detection window, the magnitude of the amplitude response fails to reach the level which is achieved when the strengths of and are matched.

5.2.3. Setting the Reference Level

As the first step of performing static characterization for the detection unit, the operating point of the window detector () is manipulated by setting the reference level with variable dc voltages (within 0.5~1.2 V). The port is fed with a ramp (linearly increasing) source and corresponding output voltages are plotted for different combinations of the two inputs. The shape of the response in Figure 8(a) suggests a dependence of the detection window on the strength of reference level. For example, when is tied to 0.69 V the detectable range for the input is uniform and approximated by 0.55~.78 V. In this case, the detection window is not perfectly symmetric around the reference level and the asymmetry may increase for wider ranges for the window. As for  V, the window covers the domain of 0.76–1.12 V and for  V, the window becomes open ended at one side. This would indicate the necessity of a suitable choice for the detection width with regard to maintaining symmetry. The next section would test the influence of the controlling parameters obtained from the expression of the decision threshold.

5.2.4. Mirror Factor

Using the control circuit implemented by , the factor can be set from 1 to 5 if these devices have the same sizes as and . Out of the parameters obtained from (17), exerts a greater influence in manipulating the detection window. By doubling the size of as compared to the dimensions of or , can be extended to a value of 10. Within this coverage, the window width can be adjusted between ±80 to ±750 mV around the reference voltage, as shown in Figure 8(b). A high value of can lead to a very wide window, causing spurious detection in the receiver. So, a suitable value for the mirror factor is chosen as 2-3 to ensure a symmetric window. This can be achieved by tying two or three of the switching signals () in Figure 3(c) to the bias supply rail ().

5.2.5. Final Response from the Back-End

The back-end of a TR-receiver starts with an RF mixer (multiplier) which is followed by the threshold detection block (see Figure 1(b)). The RF mixer response, duely processed, is turned into a driving signal for the window detector. Rather than using separate integrator, sample-hold, and threshold detection blocks, we have proposed a buffered comparator core as the basis of the detector circuit. In the most simple form, each frame in a received UWB pulse train consists of a pair of pulses or a doublet. The first pulse in the frame is employed as a “synchronizing pulse” or “reference pulse” and it is followed by a “data pulse” modulated according to the message signal. We have seen in Figure 8(a) that the proposed decision circuit provides a quasi-symmetric detection window around a reference voltage of 0.58~0.78 V. Therefore, the mixer response is processed by a wideband amplifier and a shift in its dc base is introduced by a simple resistive adder. The shifted and modified RF mixer response is fed to the decision section as shown in Figure 9(a), and the reference level is carefully selected to vary between 0.65 to 0.705 V in minute steps of 0.01 V to optimize the reference signal. The corresponding response from the comparator becomes bipolar and quasi-symmetric with respect to its dc base when approaches 0.67 V. So the iteration of is repeated, this time in even smaller steps, and the final reference limit is set to the vicinity of 0.672 V. The factor is regulated in Figure 9(b) to assess the effect of a variable mirror factor after the reference signal is already optimized. The sharp degradation of the output signal suggests that the controlling parameters in (17) should be employed in a mutually exclusive fashion. And finally, a buffer gate should be placed at the output of the threshold detection circuit to recover a regular decoded data stream.

Figure 10(a) presents the response from a buffered window detector for an input bit rate of 0.1 Gbps. The two driving signals for the RF mixer (RF and LO excitations) are plotted in the same frame to visualize the overlapping of the two inputs at instances when the decision circuits produce a positive detection. The stream corresponds to an arbitrary four-bit sequence of 1 0 1 0, with the magnitude of the Gaussian pulses falling within the range of ±300 mV. The amount of delay between the two multiplier inputs is equal to the separation between the “reference pulse” and the “data pulse”. The reference pulses of the second mixer input, after being delayed by a wideband element, become synchronized in time with the data pulses of the driving RF signal and there is no visible dispersion effect on the final responses. The signals at different stages of the proposed back-end for a TR-receiver are drawn separately in Figure 10(b), which include the input pulse streams (RF and LO) fed to a radio-frequency mixer, the base-shifted response from the mixer, the bipolar signal from the comparator (window detector), and the final response from an output buffer section. The buffer gate is implemented with a pair of cascaded inverters, producing a decoded stream from the response of the window comparator. The template data rate of the back-end circuits is tested up to 2 Gbps and at higher data rates (after 1 Gbps) the window detector performs with an inverse response, as shown in Figures 11(a) and 11(b). A certain amount of time-shift is also introduced by the logic gates existing in the design. The performance metrics of the TR front- and back-end components and their comparative standing with respect to published results are summarized in the next section.

6. Comparison of Performance

6.1. Front-End

Table 1 documents the performance of the proposed front-end double-stage 90 nm amplifier and compares it with simulated results from reported millimeter-wave front-end circuits [20, 2738]. Simulated data have been collected from the references or concerned designs have been analyzed in the authors' environment to make a fair comparison. To evaluate designs built on different platforms, a composite figure-of-merit parameter () is defined with the following equation: As indicated by a high (), the proposed design of the front-end delivers relatively high forward-gain, lower noise contribution, and a high peak gain frequency in the -band, facilitating its interfacing with the following mixer in the TR-receiver.

ReferencesGain Process Freq. Min. Min. Noise Supply IIP3 Power Core area FOM1
( , dB)(nm, CMOS)(GHz)(dB)(dB)(NF, dB)(V) ( ) (mW)(mm2)

20.5 90 22.7 −18 −24.8 3.5 1.2 −4 27.2 0.66 6.84
[20] 20 130 23.5 −12 −21.5 4.5 1.2 −5 24 0.36 5.59
[27] 23 180 16 −11 −18 6.5 1.5 28 1.32*2.39
[28] 10 180 8 <−14 <−14 4.3 0.6 2 7 3.46
[29] 9.8 180 2.3 −20 −12 4 1.3 3 9 1.16 0.83
[30] 11 180 8.9 4.15 1 7 23.5 1.32
[31] 13 130 2.2 −28 4 1.3 7 2.62 0.58 3.64
[31] 15 130 2.2 −28 4.3 1.3 1 2.6 0.58 3.85
[32] 7 65 1 −17 2.6 1.2 1 14 0.009 0.31
[33] 17 180 1 −19 2.8 2.2 4 15.8 0.67 0.59
[34] 12 130 0.6 −12.5 −14 2.3 1.5 16 17.4 0.099 0.31
[35] 15 90 1.82 −20 3.85 1 14 4 0.294/ 2.39
[36] 26 90 2 −23 −18 2.75 1 2 9 0.046 3.30
[37] 18 130 2 −23 3 1.2 −10 25 1.5*0.72
[38] 12.5 65 1 −16 −23.5 2.3 1 −3 13.7 0.02 0.70
[38] 14.5 65 1 −12.5 −15.5 2.8 1 −5 7 0.03 1.15

/Including probe pads
*For entire front-end.
6.2. Back-End

The performance of the buffered window comparator in the back-end is tabulated in Table 2, illustrating its relative merits with respect to data rate, power dissipation, speed/power ratio, and supply voltage. To quantify the relative simulated performance of the proposed decision block with respect to published detection circuits [3949], a second figure-of-merit () is defined with The table shows the contrast in the figures-of-merit achieved by pipelined analog-to-digital converters and a window comparator. These findings verify the merits of the proposed TR-receiver back-end in terms of speed and power-efficiency.

Reference Technology
(CMOS, nm)
Bias supply
Maximum speed/power (GHz/W)Capacity/sampling freq. Core area
FOM2 (from (23))

This work 90 1.2 7.536 265.39 0.1~2.0 Gbps 0.125 0.2212
[39] 130 1.8 180 8.9 1.6 GS/s 0.42 0.0049
[40] 65 1.2 110 9.1 1.0 GS/s 0.87 0.0076
[41] 65 1.2 60 16.7 1.0 GS/s 0.2 0.0139
[42] 65 1.0 40 55 2.2 GS/s 0.3 0.055
[43] 90 1.3 92 11.96 1.1 GS/s 0.37 0.0092
[44] 45 1.1 50 50 2.5 GS/s 1 0.0455
[45] 65 1.0 35 42.86 1.5 GS/s 0.5 0.0429
[46] 65 1.2 6.7 149.25 1.0 GS/s 0.11 0.1244
[47] 180 1.8 2.52 396.82 1.0 GS/s 0.2205
[48] 130 1.2 120 26.67 3.2 GS/s 0.18 0.0222
[49] 90 1.4 180 23.33 4.2 GS/s 0.66 0.0167

7. Conclusions

The subject of this paper is the implementation of front- and back-end blocks for a transmit-reference (TR) receiver using noise and power efficient architectures. A 90-nm wideband amplifier is proposed for the front-end which achieves a forward gain 20.5 dB at the center-point with a 3.3 GHz bandwidth. The peak port matching parameters stand at −18 dB and −24.8 dB whereas the amplifier behaves linearly up to a power limit of −4 d at the driving port. To support the two-stage differential structure, the front-end consumes 27.2 mW while the noise performance (NF) approaches a minimum level of 3.5 dB near the center frequency (in -band). The back-end of the TR-receiver is completed with a buffered detection circuit with a regulated decision window. Static and dynamic behavior for the detector block are tested with a variable transmit-reference pulse stream (0.1~2 Gbps). For each unit of consumed power, the achieved speed of the window detector covers a range of 14 to 265.4 GHz. The proposed architectures fare better when compared with published designs of their counterparts and should help the on-chip realization of a TR-receiver.


The author would like to thank S. Rashid, Dr. H. Rashid, and the authority of Bangladesh University of Engineering and Technology.


  1. B. Park, K. Lee, and S. Choi, “A receiver front-end design in 0.13 μm CMOS for multiband OFDM UWB system,” in Proceedings of the Asia Pacific Microwave Conference (APMC '09), pp. 241–244, December 2009. View at: Publisher Site | Google Scholar
  2. C. W. Kim, M. S. Kang, P. T. Anh, H. T. Kim, and S. G. Lee, “An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system,” IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp. 544–547, 2005. View at: Publisher Site | Google Scholar
  3. A. Ismail and A. A. Abidi, “A 3.1- To 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-μm SiGe BiCMOS for mode-2 MB-OFDM UWB communication,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2573–2582, 2005. View at: Publisher Site | Google Scholar
  4. M. C. Ha, Y. J. Park, and Y. S. Eo, “A 3–5 GHz non-coherent IR-UWB receiver,” Journal of Semiconductor Technology and Science, vol. 8, no. 4, pp. 277–282, 2008. View at: Google Scholar
  5. Q. H. Dang, A. Trindade, A. J. Van Der Veen, and G. Leus, “Signal model and receiver algorithms for a transmit-reference ultra-wideband communication system,” IEEE Journal on Selected Areas in Communications, vol. 24, no. 4, pp. 773–779, 2006. View at: Publisher Site | Google Scholar
  6. M. R. Casu and G. Durisi, “Implementation aspects of a transmitted-reference UWB receiver,” Wireless Communications and Mobile Computing, vol. 5, no. 5, pp. 537–549, 2005. View at: Publisher Site | Google Scholar
  7. B. Leung, VLSI for Wireless Communication, Prentice Hall, India, New Delhi, 1st edition, 2002.
  8. A. Roy, S. M. S. Rashid, M. A. Arafat, and A. B. M. H. Rashid, “Design of a wideband delay element for transmitted reference UWB receivers,” in Proceedings of the 6th International Conference on Electrical and Computer Engineering (ICECE '10), pp. 97–100, December 2010. View at: Publisher Site | Google Scholar
  9. Z.-Y. Huang, “A Ka-band CMOS low-noise amplifier for Ka-band communication system,” in Proceedings of the World Congress on Engineering and Computer Science, pp. 1–4, October 2010. View at: Google Scholar
  10. Y.-C. Chen, C. H. Wang, and Y.-S. Lin, “Low-power 24 GHz CMOS receiver front-end using isolation enhancement technique for automatic radar systems,” Microwave and Optical Technology Letters, vol. 54, no. 6, pp. 1471–1476, 2012. View at: Google Scholar
  11. T. P. Wang, “A low-voltage low-power K-band CMOS LNA using DC-current-path split technology,” IEEE Microwave and Wireless Components Letters, vol. 20, no. 9, pp. 519–521, 2010. View at: Publisher Site | Google Scholar
  12. F. S. Mitra, “On optimal data detection for UWB transmitted reference system,” in Proceedings of the Global Telecommunications Conference, pp. 764–768, San Francisco, Calif, USA, December 2003. View at: Google Scholar
  13. R. T. Hoctor and H. W. Tomlinson, “Delay-hopped transmitted reference RF communications,” in Proceedings of the IEEE Conference on Ultra Wideband Systems and Technologies, pp. 265–270, Baltimore, Md, USA, 2002. View at: Google Scholar
  14. A. Schranzhofer, Y. Wang, and A. J. Van Der Veen, “Acquisition for a transmitted reference UWB receiver,” in Proceedings of the IEEE International Conference on Ultra-Wideband (ICUWB '08), pp. 149–152, September 2008. View at: Publisher Site | Google Scholar
  15. Q. H. Dang and A. J. van der Veen, “A decorrelating multiuser receiver for transmit-reference UWB systems,” IEEE Journal on Selected Topics in Signal Processing, vol. 1, no. 3, pp. 431–442, 2007. View at: Publisher Site | Google Scholar
  16. Q. H. Dang, A. Trindade, A. J. Van Der Veen, and G. Leus, “Signal model and receiver algorithms for a transmit-reference ultra-wideband communication system,” IEEE Journal on Selected Areas in Communications, vol. 24, no. 4, pp. 773–779, 2006. View at: Publisher Site | Google Scholar
  17. J. Foerster, “Report on channel modeling,” IEEE P802.15 standard for Wireless Personal Area Networks, 2005. View at: Google Scholar
  18. H. K. Chiou, H. Y. Liao, and K. C. Liang, “Compact and low power consumption K-band differential low-noise amplifier design using transformer feedback technique,” IET Microwaves, Antennas and Propagation, vol. 2, no. 8, pp. 871–879, 2008. View at: Publisher Site | Google Scholar
  19. M. El-Nozahi, A. A. Helmy, E. Sánchez-Sinencio, and K. Entesari, “An inductor-less noise-cancelling broadband low noise amplifier with composite transistor pair in 90 nm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 46, no. 5, pp. 1111–1122, 2011. View at: Publisher Site | Google Scholar
  20. X. Guo and K. K. O, “A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 9, pp. 603–605, 2005. View at: Publisher Site | Google Scholar
  21. K. W. Yu, Y. Lu, D. Huang, D. C. Chang, V. Liang, and M. F. Chang, “A 26 GHz low-noise amplifier in 0.18μm CMOS technology,” in Proceedings of the IEEE International Symposium on Electron Devices Microwave Optoelectronic Applications, pp. 93–98, 2003. View at: Google Scholar
  22. S. M. Shahriar Rashid, A. Roy, S. N. Ali, and A. B. M. H. Rashid, “Design of A 21 GHz UWB differential low noise amplifier using .13μm CMOS process,” in Proceedings of the 12th International Symposium on Integrated Circuits (ISIC '09), pp. 538–541, December 2009. View at: Google Scholar
  23. D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 745–759, 1997. View at: Google Scholar
  24. H. Samavati, H. R. Rategh, and H. Lee Thomas, “A 5-GHz CMOS wireless LAN receiver front end,” IEEE Journal of Solid-State Circuits, vol. 35, no. 5, pp. 765–772, 2000. View at: Google Scholar
  25. A. Laknaur, R. Xiao, and H. Wang, “A programmable window comparator for analog online testing,” in Proceedings of the 25th IEEE VLSI Test Symposium (VTS '07), pp. 119–124, May 2007. View at: Publisher Site | Google Scholar
  26. A. Roy, “A window detection technique with adjustable threshold for transmitted reference receivers,” submitted to Central European Journal of Engineering. View at: Google Scholar
  27. B. A. Floyd, L. Shi, Y. Taur, I. Lagnado, and K. K. O, “A 15-GHz wireless interconnect implemented in a 0.18-μm CMOS technology using integrated transmitters, receivers, and antennas,” in Proceedings of the VLSI Circuits Symposium, pp. 155–158, June 2001. View at: Google Scholar
  28. Y. H. Yu, Y. J. E. Chen, and D. Heo, “A 0.6-V low power UWB CMOS LNA,” IEEE Microwave and Wireless Components Letters, vol. 17, no. 3, pp. 229–231, 2007. View at: Publisher Site | Google Scholar
  29. F. Zhang and P. R. Kinget, “Low-power programmable gain CMOS distributed LNA,” IEEE Journal of Solid-State Circuits, vol. 41, no. 6, pp. 1333–1343, 2006. View at: Publisher Site | Google Scholar
  30. R. L. Wang, M. C. Lin, C. F. Yang, and C. C. Lin, “A IV 3.1-10.6 GHz full-band cascoded UWB LNA with resistive feedback,” in Proceedings of the IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC '07), pp. 1021–1023, December 2007. View at: Publisher Site | Google Scholar
  31. H. Zhang, X. Fan, and E. S. Sinencio, “A low-power, linearized, ultra-wideband LNA design technique,” IEEE Journal of Solid-State Circuits, vol. 44, no. 2, pp. 320–330, 2009. View at: Publisher Site | Google Scholar
  32. S. C. Blaakmeer, E. A. M. Klumperink, D. M. W. Leenaerts, and B. Nauta, “Wideband balun-LNA with simultaneous output balancing, noise-canceling and distortion-canceling,” IEEE Journal of Solid-State Circuits, vol. 43, no. 6, pp. 1341–1350, 2008. View at: Publisher Site | Google Scholar
  33. D. Im, I. Nam, H. T. Kim, and K. Lee, “A wideband CMOS low noise amplifier employing noise and IM2 distortion cancellation for a digital TV tuner,” IEEE Journal of Solid-State Circuits, vol. 44, no. 3, pp. 686–698, 2009. View at: Publisher Site | Google Scholar
  34. W. H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A highly linear broadband CMOS LNA employing noise and distortion cancellation,” IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1164–1175, 2008. View at: Publisher Site | Google Scholar
  35. G. Zare Fatin, Z. D. Koozehkanani, and H. Sjöland, “A 90 nm CMOS + 11 dbm IIP3 4 mW dual-band LNA for cellular handsets,” IEEE Microwave and Wireless Components Letters, vol. 20, no. 9, pp. 513–515, 2010. View at: Publisher Site | Google Scholar
  36. H.-C. Lee, C. -Shiun Wang, and C. -Kuang Wang, “A 0.22.6 GHz wideband noise-reduction Gm-boosted LNA,” IEEE Microwave and Wireless Components Letters, vol. 22, pp. 269–271, 2012. View at: Google Scholar
  37. X. Wang, J. Sturm, and N. Yan, “0.63-GHz wideband receiver RF front-end with a feedforward noise and distortion cancellation resistive-feedback LNA,” IEEE Tranactions on Microwave Theory and Techniques, vol. 60, pp. 387–392, 2012. View at: Google Scholar
  38. K. H. Chen and S. I. Liu, “Inductorless wideband CMOS low-noise amplifiers using noise-canceling technique,” IEEE Transactions on Circuits and Systems I, vol. 59, pp. 305–314, 2012. View at: Google Scholar
  39. A. Ismail and M. Elmasry, “A 6-bit 1.6-GS/s low-power wideband flash ADC converter in 0.13-μm CMOS technology,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 1982–1990, 2008. View at: Publisher Site | Google Scholar
  40. D. Choi, D. Kim, K. Cho, D. Kim, and M. Song, “A low noise 65nm 1.2V 7-bit 1GSPS CMOS folding A/D converter with a digital self-calibration technique,” in Proceedings of the International SoC Design Conference (ISOCC '10), pp. 194–197, November 2010. View at: Publisher Site | Google Scholar
  41. J. Lee, B. C. Michael, H. J. Park, and B. H. Park, “A 7b 1GS/s 60mW folding ADC in 65nm CMOS,” in Proceedings of the International SoC Design Conference (ISOCC '10), pp. 338–341, November 2010. View at: Publisher Site | Google Scholar
  42. I.-N. Ku, Z. Xu, Y.-C. Kuan, Y.-H. Wang, and M.-C. Frank Chang, “A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 1–4, September 2011. View at: Google Scholar
  43. C. C. Hsu, C. C. Huang, Y. H. Lin et al., “A 7b 1.1GS/s reconfigurable time-interleaved ADC in 90nm CMOS,” in Proceedings of the Symposium on VLSI Circuits (VLSIC '07), pp. 66–67, June 2007. View at: Publisher Site | Google Scholar
  44. E. Alpman, H. Lakdawala, L. R. Carley, and K. Soumyanath, “A 1.1V 50mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45nm LP digital CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '09), pp. 76–78, February 2009. View at: Publisher Site | Google Scholar
  45. J. Proesel, G. Keskin, J. O. Plouchart, and L. Pileggi, “An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection,” in Proceedings of the 32nd Annual Custom Integrated Circuits Conference (CICC '10), pp. 1–4, September 2010. View at: Publisher Site | Google Scholar
  46. J. Yang, T. L. Naing, and B. Brodersen, “A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '09), pp. 287–290, September 2009. View at: Publisher Site | Google Scholar
  47. R. C. Taft, P. A. Francese, M. R. Tursi et al., “A 1.8 V 1.0 GS/s 10b self-calibrating unified-folding-interpolating ADC With 9.1 ENOB at nyquist frequency,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3294–3304, 2009. View at: Publisher Site | Google Scholar
  48. Y. Z. Lin, C. W. Lin, and S. J. Chang, “A 5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 3, pp. 509–513, 2010. View at: Publisher Site | Google Scholar
  49. S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, “A 3.5 GS/s 5-b flash ADC in 90 nm CMOS,” in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference (CICC '06), pp. 489–492, September 2006. View at: Publisher Site | Google Scholar

Copyright © 2012 Apratim Roy. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

More related articles

 PDF Download Citation Citation
 Download other formatsMore
 Order printed copiesOrder

Related articles

We are committed to sharing findings related to COVID-19 as quickly as possible. We will be providing unlimited waivers of publication charges for accepted research articles as well as case reports and case series related to COVID-19. Review articles are excluded from this waiver policy. Sign up here as a reviewer to help fast-track new submissions.