International Scholarly Research Notices

International Scholarly Research Notices / 2013 / Article

Research Article | Open Access

Volume 2013 |Article ID 914058 | 7 pages | https://doi.org/10.1155/2013/914058

High-Frequency and Low-Power Output Stages Based on FGMOS Flipped Voltage Follower

Academic Editor: C. W. Chiou
Received29 Nov 2012
Accepted25 Dec 2012
Published10 Feb 2013

Abstract

Two new high-performance output stages are proposed. These output stages are basically designed by using a flipped voltage follower (FVF). The proposed low-power and low-voltage output stages have utilized the advantages of the FGMOS technology. They are characterized by low-power dissipation, reduced power supply requirement, and larger bandwidth. By using FGMOS-based FVF in place of conventional FVF, the linearity of the output stages has been highly improved. The small-signal analysis of FGMOS-based FVF is done to show the bandwidth enhancement of conventional FVF. The circuits are simulated to demonstrate the effectiveness using SPICE, in TSMC 0.25-micron CMOS device models. The simulation results show that the power supply requirement of the proposed output stages is highly reduced and bandwidths are extremely higher than the conventional circuits.

1. Introduction

The challenge of designing of high performance low-voltage and low-power analog circuits is increasing due to the scaling down of CMOS technology and the increasing demand for portable electronic equipments [1]. The speed of conventional analog integrated circuits is degrading on reducing the supply voltage for a given technology. To fulfill these requirements, the researchers are focusing on the development of new integrated circuits that have low voltage supply requirement, without any degradation in the performance.

One of the basic building blocks in analog signal processing circuits is voltage buffer, which is used to drive low-impedance loads (Figure 1(a)). The flipped voltage follower (FVF) [2] is a low-voltage operating buffer that can be used in different circuits in place of conventional voltage buffer very efficiently. A FVF circuit is shown in Figure 1(b).

A FVF cell has found increasing applications in areas where a voltage buffer is required. These applications include operational amplifier, current mirror, output stages, and arithmetic circuits and act as a basic building block in various analog circuits [27]. The advantages of FVF include low supply voltage requirement, almost unity gain, and high current-sinking capabilities [2].

Ramirez-Angulo et al. [3] have introduced an FVF which is based on FGMOS level shifter stage, shown in Figure 2. Due to its high swing and low voltage operation, the FGMOS-based FVF can be preferred over conventional FVF in many high-swing, low-power, and wideband analog integrated circuits.

Applications for communication systems require low power, low voltage, and high frequency output stages. The supply voltage and the power dissipation of output stage can be reduced by using floating gate technology. There are several attractive features of FGMOS such as it can incorporate tuneable mechanisms and work below the operational limits of supply voltage levels for a particular technology, without affecting the other characteristics of the system, and thus power dissipation is also lesser than the minimum power required for a MOS circuit of the same technology [813].

Usually buffers require an extra circuitry to achieve large bandwidth, which often increases power consumption. In this work, the FVF with floating gate level shifter [3] is used to replace the conventional FVF in different output stages, which have been investigated by Centurelli et al. in [14]. We have achieved high bandwidth of output stages, without affecting the gain of the system, and moreover the power consumption is highly reduced.

This paper is organized as follows. Section 2 covers the large signal analysis and small signal analysis of conventional FVF with a floating gate level shifter. Section 3 presents the proposed output stages based on FGMOS FVF. On the basis of simulation results, the performances of designed circuits are compared in Section 4. Finally, the conclusion is given in Section 5.

2. FVF with Floating Gate Level Shifter

2.1. Large Signal Analysis

The symbolic representation of two-input floating gate transistor, whose threshold voltage can be controlled by the values of capacitors, and its equivalent circuit are shown in Figures 3(a) and 3(b), respectively.

The input signal () and bias () are applied at gate G1 and G2, respectively. The drain current () of the FGMOS operating in ohmic region is given by [8, 9] where is the transconductance parameter, and are the capacitances associated with G1 and G2, is the total floating-gate (FG) capacitance, and stands for the threshold voltage. The above equation can be simplified as where effective threshold voltage () is given by [8]

From (3), it is obvious that the reduction in can be done by selecting and . Hence, is controllable and it depends on the values of and . The proposed output stage circuits utilize this property of the FGMOS transistor.

The control gates (G1 and G2) develop a floating gate voltage as a weighted sum of inputs voltages , via a capacitive voltage divider. is given by [8] where is the voltage at terminal, , , and are the parasitic capacitances, is capacitance at input, terminal, is the total capacitance seen by floating gate and refers to the amount of charge that has been trapped in floating gate during fabrication. Using (4) to find the floating gate voltage of FGMOS-based FVF (Figure 2) and an approximation given in [8], we obtain or Hence, the voltage at drain terminal of M1 is It is obvious from (7) that is level shifted by .

2.2. Small Signal Analysis

The small signal model of FGMOS-based FVF is shown in Figure 4. The FGMOS-based FVF is analyzed to obtain the transfer function.

In the analysis, and are the resistances due to channel length modulation effect, and are the gate to source capacitances, and and are the transconductances of transistors M1 and M2, respectively. and are the capacitances associated with two different inputs of floating gate transistor M2, respectively, and is the output impedance of the current source .

On applying KCL at nodes (a), (b), and (c) in Figure 4, the obtained equations are where .

Substituting the value of from (10) in (9), it gives And, thus, Replacing by using (12) in (8), the transfer function is given by where .

Assuming , , and , (13) transforms into where By definition, at , [16], and thus The −3 dB frequency is (Since the expression of the lower 3-dB frequency is too large, the symbols are used to represent it.) By placing the values of symbols, it can be easily observed that the lower 3-dB frequency of floating gate FVF is much greater than that of simple FVF [7].

To enhance the speed and reduce the power supply requirement, the wideband FGMOS-based FVF is used in conventional buffers [14] and is explained in the next section.

3. Proposed High-Frequency and Low-Power Output Stages

In many analog circuits, it is required to drive the impedance by a voltage buffer like that in operational amplifiers. For low-power circuits, low-power voltage buffers are used as output stages. The FVF has overcome the drawbacks of conventional voltage buffers. It has low-power dissipation, large output signal swing, low settling time, and almost unity gain [2]. Moreover, class AB biasing can be employed to reduce power consumption without affecting the ability to drive large capacitive loads [14]. Figure 5 shows an output stage based on conventional FVF [15]. But a FVF will not work properly in class AB. Centurelli et al. [14] have developed an output stage which was based on FVF operating in class AB (Figure 6).

In this paper, we have introduced two output stages which are based on FVF with FGMOS level shifter. The proposed output stages are shown in Figures 7 and 8.

The output stage shown in Figure 8 operates in class AB. It is shown in Section 2.2 that a FVF with a floating gate level shifter has larger bandwidth in comparison to the conventional FVF. This motivates us to replace MOS transistor M2 by a two-input FGMOS transistor. Moreover, the proposed circuits have high linearity, low power consumption, and power supply requirement.

The effects and advantages of replacing conventional transistor by floating gate transistor can be easily observed through the simulation results.

4. Simulation Results

The designed circuits are simulated using PSPICE in TSMC 0.25 um CMOS technology. The FGMOS circuits have been simulated by using the model given by EdgarSánchez-Sinencio [9].

In this work, the performance of a simple FVF and floating-gate-based FVF is compared. The circuit parameters of simple FVF and FGMOS-based FVF are given in Table 1.


ParametersValues

Aspect ratio of M1(10/0.25) μm
Aspect ratio of M2(10/1) μm
Bias current 500 μA
FGMOS capacitors 175 fF
FGMOS resistors 10 G

It is obvious from the DC response (shown in Figure 9) that, by using floating gate transistor in place of MOS transistor, the linearity and gain of the system have been improved.

Figure 10 shows the frequency responses of these two circuits. The bandwidth is extended from 1.17 GHz to 4.78 GHz.

The paper has presented two new buffers that can be used as output stage in many analog and mixed-signal circuits. The circuit parameters of FVF-based output buffer and class AB output buffers are given in Tables 2 and 3, respectively.


ParametersValues

Aspect ratio of M1 and M2(13/0.25) μm
Aspect ratio of M3(100/0.5) μm
Aspect ratio of M4 and M5(50/0.5) μm
Bias voltage = 0.3 V
Bias voltage 0.2 V
FGMOS capacitors 175 fF
FGMOS resistors 10 G


ParametersValues

Aspect ratio of M1 and M2(2/0.25) μm
Aspect ratio of M3 and M4(3/0.25) μm
Aspect ratio of M5 and M6(15/0.25) μm
Aspect ratio of M7(1/0.25) μm
Bias voltage 1 V
Bias voltage 0.2 V
FGMOS capacitors 175 fF
FGMOS resistors 10 GΩ

The DC responses of the proposed and conventional buffer circuits are shown in Figures 11 and 12. The use of FGMOS technology has improved the linearity of the buffers to a large extent and power consumption is reduced. The frequency responses of the conventional and proposed buffers are shown in Figures 13 and 14.

The level shifting in output signal can be easily observed in the proposed circuits. The bandwidth has been largely enhanced by using floating-gate-based FVF. The comparative results are given in Table 4.


Simulated circuitPower supply (V)Output impedance (Ω)Voltage gainPower dissipation (mW)

Simple FVF3.054.340.911.5
Conv. FGMOS-based FVF1.065.090.950.5
Conv. FVF-based output stage 3.052.820.891.18
Prop. FVF-based output stage0.851.450.910.0062
Conv. class AB FVF buffer3.0196.910.931.22
Prop. class AB FVF buffer1.8106.710.990.071

5. Conclusion

In this paper, two new low-power low-voltage and wideband output stages based on FVF with floating gate level shifter have been proposed. The use of floating gate technology provides the advantages of low-power consumption and low-power supply requirement. Moreover it gives a significant improvement in the bandwidth of the systems and the ability of the buffers to drive heavy capacitive loads by decreasing the output impedance. The simulation results have shown that the proposed buffers display good characteristics when compared with the reported works achieved so far. These improved buffer structures can be useful as output stage in many analog signal processing applications.

References

  1. S. S. Mohan, M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, “Bandwidth extension in CMOS with optimized on-chip inductors,” IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 346–355, 2000. View at: Publisher Site | Google Scholar
  2. R. G. Carvajal, J. Ramirez-Angulo, A. L. Martin et al., “The flipped voltage follower: a useful cell for low voltage low power circuit design,” IEEE Transactions on Circuits and Systems I, vol. 52, no. 7, pp. 1276–1279, 2005. View at: Publisher Site | Google Scholar
  3. J. Ramírez-Angulo, S. Gupta, I. Padilla et al., “Comparison of conventional and new flipped voltage structures with increased input/output signal swing and current sourcing/sinking capabilites,” in Proceedings of the IEEE International 48th Midwest Symposium on Circuits and Systems (MWSCAS '05), pp. 1151–1154, August 2005. View at: Publisher Site | Google Scholar
  4. J. Ramirez-Angulo, R. G. Carvajal, A. Torralba, J. Galan, A. P. Vega-Leal, and J. Tombs, “Low-power low-voltage analog electronic circuits using the flipped voltage follower,” in Proceedings of the IEEE International Symposium on Industrial Electronics, pp. 1327–1330, May 2002. View at: Google Scholar
  5. C. Sakul and K. Dejhan, “Squaring and square-root circuits based on flipped voltage follower and applications,” International Journal of Information Systems and Telecommunication Engineering, vol. 1, pp. 19–24, 2010. View at: Google Scholar
  6. C. Koliopoulos and C. Psychalinos, “A comparative study of the performance of the flipped voltage follower based low-voltage current mirrors,” in Proceedings of the International Symposium On Signals, Circuits and Systems (ISSCS '07), vol. 1, pp. 1–4, Iasi, Romania, July 2007. View at: Publisher Site | Google Scholar
  7. M. Gupta and U. Singh, “A new flipped voltage follower with enhanced bandwidth and low output impedance,” Analog Integrated Circuits & Signal Processing, vol. 72, no. 1, pp. 279–288, 2012. View at: Publisher Site | Google Scholar
  8. E. R. Villegas, Low Power and Low Voltage Circuit Design With the FGMOS Transistor, IEE Circuits, Devices and Systems Series, The Institution of Engineering and Technology, London, UK, 2006.
  9. E. Sánchez-Sinencio, “Floating Gate Techniques and Applications,” 2012, http://amesp02.tamu.edu/~sanchez/607-2010-Floating%20Gate%20Circuits.pdf. View at: Google Scholar
  10. S. S. Rajput and S. S. Jamuar, “Design techniques for low voltage analog circuit structures,” in Proceedings of the IEEE National Symposiumon Microelectronic (NSM '01), pp. 49–52, Genting Highlands, Malaysia, 2001. View at: Google Scholar
  11. S. Sharma, S. S. Rajput, L. K. Mangotra, and S. S. Jamuar, “FGMOS current mirror: behaviour and bandwidth enhancement,” Analog Integrated Circuits & Signal Processing, vol. 46, no. 3, pp. 281–286, 2006. View at: Publisher Site | Google Scholar
  12. A. J. Lopez-Martin, J. Ramírez-Angulo, R. G. Carvajal, and L. Acosta, “CMOS transconductors with continuous tuning using FGMOS balanced output current scaling,” IEEE Journal of Solid-State Circuits, vol. 43, no. 5, pp. 1313–1323, 2008. View at: Publisher Site | Google Scholar
  13. R. Pandey and M. Gupta, “FGMOS based tunable grounded resistor,” Analog Integrated Circuits & Signal Processing, vol. 65, no. 3, pp. 437–443, 2010. View at: Publisher Site | Google Scholar
  14. F. Centurelli, P. Monsurro, and A. Trifiletti, “A class-AB flipped voltage follower output stage,” in Proceedings of the 20th European Conference on Circuit Thoery and Design (ECCTD '11), pp. 757–760, Rome, Italy, 2011. View at: Google Scholar
  15. M. Jiménez, A. Torralba, R. G. Carvajal, and J. Ramirez-Angulo, “A new low-voltage CMOS unity-gain buffer,” in Proceedings of the 2006 IEEE International Symposium on Circuits and Systems (ISCAS '06), pp. 919–922, May 2006. View at: Google Scholar
  16. A. S. Sedra and K. C. Smith, Microelectronics Circuits, Oxford University Press, New York, NY, USA, 5th edition, 2005.

Copyright © 2013 Maneesha Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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