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Journal of Applied Mathematics
Volume 2014, Article ID 194574, 15 pages
Research Article

Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions

1School of Computer and Information Technology, Beijing Jiaotong University, Beijing 10044, China
2School of Electronic and Information Engineering, Lanzhou Jiaotong University, Lanzhou 730070, China
3G & S Labs, School of Software of Dalian University of Technology, Dalian 116620, China
4Guangxi Key Laboratory of Hybrid Computation and IC Design Analysis, Guangxi University for Nationalities, Nanning 530006, China

Received 13 February 2014; Accepted 7 April 2014; Published 11 June 2014

Academic Editor: Xiaoyu Song

Copyright © 2014 Ning Zhou et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We introduce an approach exploiting the power of polynomial ring algebra to perform SystemVerilog assertion verification over digital circuit systems. This method is based on Groebner bases theory and sequential properties checking. We define a constrained subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using Groebner bases for concurrent SVAs checking. Case studies show that computer algebra can provide canonical symbolic representations for both assertions and circuit designs and can act as a novel solver engine from the viewpoint of symbolic computation.