Research Article
Groebner Bases Based Verification Solution for SystemVerilog Concurrent Assertions
Input: | (1) circuit model ; | (2) initial condition ; | (3) an assertion ; | Output: Boolean: or ; | BEGIN | /*Step 1: initialize input signals via testbench */ | (00) ; | (01) ; | /*Step 2: build polynomial model */ | (02) ; | /*Step 3: build polynomial set for initial condition */ | (03) ; | /*Step 4: build polynomial set for consequent */ | (04) ; | /*Step 5: calculate the */ | (05) ; | /*Step 6: calculate the Groebner base of */ | (06) ; | /*Step 7: determine the basis is or not */ | (07) if() { | (08) return ; } | /*Step 8: check every polynomial */ | /**/ | (09) ; | (10) { | (11) if() { | (12) return ; } | (13) i++; | (14) } /* endwhile */ | (15) return ; /* Assertion does hold */ | END; |
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