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Journal of Applied Mathematics
Volume 2014, Article ID 197252, 9 pages
Research Article

Functional Verification of High Performance Adders in COQ

1School of Software, Tsinghua University, Beijing 100084, China
2Department of ECE, Portland State University, Portland, OR 97207, USA

Received 3 January 2014; Accepted 10 February 2014; Published 10 April 2014

Academic Editor: Krishnaiyan Thulasiraman

Copyright © 2014 Qian Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Addition arithmetic design plays a crucial role in high performance digital systems. The paper proposes a systematic method to formalize and verify adders in a formal proof assistant COQ. The proposed approach succeeds in formalizing the gate-level implementations and verifying the functional correctness of the most important adders of interest in industry, in a faithful, scalable, and modularized way. The methodology can be extended to other adder architectures as well.