An Efficient Biobjective Heuristic for Scheduling Workflows on Heterogeneous DVS-Enabled Processors

Table 1

Voltage relative speed pairs.

Level	pc0		pc1		pc2
	Voltage (𝑣𝑘)	Speed (%)	Voltage (𝑣𝑘)	Speed (%)	Voltage (𝑣𝑘)	Speed (%)
0	1.60	100	1.20	100	2.00	100
1	1.40	85	1.10	90	1.70	80
2	1.20	70	1.00	80	1.40	60
3	1.00	55	0.90	70	1.10	40
4	0.80	40	0.80	60
5			0.70	50