Formal Specification Based Automatic Test Generation for Embedded Network Systems

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="909762.fig.009a" src="https://static.hindawi.com/articles/jam/volume-2014/909762/figures/909762.fig.009a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>The main interface for generating test cases.</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="909762.fig.009b" src="https://static.hindawi.com/articles/jam/volume-2014/909762/figures/909762.fig.009b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>The interface for generating test sequences.</td></tr></table></td></tr></table>

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Journal of Applied Mathematics

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Figure 9

Figure 9: Formal Specification Based Automatic Test Generation for Embedded Network Systems 