Multimode Flex-Interleaver Core for Baseband Processor Platform

Table 1

List of algorithms and permutations in different interleaver implementations and the cost comparison.

Standard	Interleaver type	Algorithm/permutation methodology	HW cost
			Addr. Gen.	Data memory
			@65 nm	@6 soft bits
			()	(kbits)
HSPA+	BTC	Multistep computation including intra-row permutation computation	12816	59.92
		;  ;
		; ;
		;
	1st, 2nd, and HS-DSCH int.	Standard block interleaving with given column permutations.	2288	29.96
		LTE	QPP for BTC		3744	72.0
Sub-Blk. int.	Standard block interleaving with given column permutations.		2080	36.0
WiMAX	Channel interleaver	Two step permutation	8944	9.0
		;
		Blk. int. b/w RS & CC	Standard block interleaver without any permutations	2080	19.92
	CTC interleaver	; ;	7280	56.25
		;
	WLAN	Channel interleaver	Two step permutation	8944	1.68
;
802.11n			Ch. Interleaver with frequency rotation	Two step permutation as above, with extra frequency interleaving, that is,	11563	24.54
	DVB-H	Outer conv. interleaver		Permutation defined by depth of first FIFO branch (M) and number of total braches.	12272	8.76
Inner bit interleaver		Six parallel interleavers with different cyclic shift	3120	0.738
		; where
Inner symbol interleaver		for even symbols; for odd symbols;	3536	35.4
		where ;
General purpose use	Row or/and Col. Perm. Given	Standard block interleaver with or without row or/and column permutation.	3952	24.0
Total cost	(all)	Independent implementations
This work	Reconfigurable Solution	HW Multiplexed Design	27757	72.0