Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System

Table 1

(a) FLP-16—half precision floating point formation (FLP-16), (b) LNS-16—Q5.11 format for logarithmic numbers.

(a)

Sign (1 bit)

Exponent (5 bits)

Mantissa (10 bits)

(b)

Sign (1 bit)

Integer (5 bits)

Fraction (10 bits)