Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System

Table 5

FAU control logic truth tables.

(a) Add/Sub = 0 (subtraction)

Inputs			Outputs
				(Add/Sub)MAN
0	0	0	0	0
0	0	1	1	0
0	1	0	0	1
0	1	1	0	1
1	0	0	1	1
1	0	1	1	1
1	1	0	0	0
1	1	1	1	0

(b) Add/Sub = 1 (addition)

Inputs			Outputs
				(Add/Sub)MAN
0	0	0	0	1
0	0	1	0	1
0	1	0	0	0
0	1	1	1	0
1	0	0	0	0
1	0	1	1	0
1	1	0	1	1
1	1	1	1	1