Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System

Table 7

Gate utilization report for each unit.

Units	Area	Percentage
Logic	66156.165	72.1%
Inverter	2318.648	2.5%
Sequential elements	22865.675	24.9%
Clock gating elements	427.745	0.5%
SFU	91768.234	100%