Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System

Table 9

Comparison of results in terms of area.

Units	Gates [9]	Gates [this work]	Gate reduction
SFU	23230	7450	67.9%
LAU	5170	3738	27.7%
FAU	3690	396	89.26%
ALOGC	3880	1092	71.85%
LOGC	7830	2224	71.5%