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Journal of Computer Networks and Communications
Volume 2015, Article ID 697153, 12 pages
http://dx.doi.org/10.1155/2015/697153
Research Article

A Mac Protocol Implementation for Wireless Sensor Network

1EµE Laboratory, Faculty of Science of Monastir, 5019 Monastir, Tunisia
2Al-Jumum University College, Umm Al-Qura University, P.O. Box 715, Makkah 21421, Saudi Arabia

Received 5 December 2014; Accepted 7 March 2015

Academic Editor: Liansheng Tan

Copyright © 2015 Jamila Bhar. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

IEEE 802.15.4 is an important standard for Low Rate Wireless Personal Area Network (LRWPAN). The IEEE 802.15.4 presents a flexible MAC protocol that provides good efficiency for data transmission by adapting its parameters according to characteristics of different applications. In this research work, some restrictions of this standard are explained and an improvement of traffic efficiency by optimizing MAC layer is proposed. Implementation details for several blocks of communication system are carefully modeled. The protocol implementation is done using VHDL language. The analysis gives a full understanding of the behavior of the MAC protocol with regard to backoff delay, data loss probability, congestion probability, slot effectiveness, and traffic distribution for terminals. Two ideas are proposed and tested to improve efficiency of CSMA/CA mechanism for IEEE 802.15.4 MAC Layer. Primarily, we dynamically adjust the backoff exponent (BE) according to queue level of each node. Secondly, we vary the number of consecutive clear channel assessment (CCA) for packet transmission. We demonstrate also that slot compensation provided by the enhanced MAC protocol can greatly avoid unused slots. The results show the significant improvements expected by our approach among the IEEE 802.15.4 MAC standards. Synthesis results show also hardware performances of our proposed architecture.