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Journal of Engineering
Volume 2013, Article ID 307451, 6 pages
Research Article

Impact of Split Gate in a Novel SOI MOSFET (SPG SOI) for Reduction of Short-Channel Effects: Analytical Modeling and Simulation

Electrical Engineering Department, Semnan University, Semnan, Iran

Received 6 October 2012; Revised 15 January 2013; Accepted 23 January 2013

Academic Editor: Daniela Munteanu

Copyright © 2013 Mohammad K. Anvarifard and Ali A. Orouji. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • Vimal Kumar Mishra, and R. K. Chauhan, “Area efficient layout design of CMOS circuit for high-density ICs,” International Journal of Electronics, pp. 1–15, 2017. View at Publisher · View at Google Scholar
  • Meysam Zareiee, “A new architecture of the dual gate transistor for the analog and digital applications,” AEU - International Journal of Electronics and Communications, 2019. View at Publisher · View at Google Scholar