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Journal of Engineering
Volume 2013, Article ID 646214, 11 pages
http://dx.doi.org/10.1155/2013/646214
Research Article

Static Switching Dynamic Buffer Circuit

Department of Electronics and Communication, MNNIT, Allahabad 211004, India

Received 20 October 2012; Revised 18 February 2013; Accepted 19 February 2013

Academic Editor: Jiun-Wei Horng

Copyright © 2013 A. K. Pandey et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We proposed footless domino logic buffer circuit. It minimizes redundant switching at the dynamic and the output nodes. The proposed circuit avoids propagation of precharge pulse to the output node and allows the dynamic node which saves power consumption. Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. Our proposed circuit reduces power consumption and power delay product as compared to the existing circuits.