Journal of Engineering / 2013 / Article / Tab 2

Research Article

Static Switching Dynamic Buffer Circuit

Table 2

Pre- and postlayout simulations results for power, delay, and PDP of the standard domino circuit and the proposed circuit for 0.18 μm standard CMOS technology.

TypePower ( W)Delay (ps)PDP (fJ)

PrelayoutStandard domino circuit444.2231.7102.9
The proposed circuit 118.6240.228.4

PostlayoutStandard domino circuit454.7238.4108.4
The proposed circuit 129.1246.131.7