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Journal of Engineering
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2013
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Article
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Tab 2
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Research Article
Static Switching Dynamic Buffer Circuit
Table 2
Pre- and postlayout simulations results for power, delay, and PDP of the standard domino circuit and the proposed circuit for 0.18
μ
m standard CMOS technology.
Type
Power (
W)
Delay (ps)
PDP (fJ)
Prelayout
Standard domino circuit
444.2
231.7
102.9
The proposed circuit
118.6
240.2
28.4
Postlayout
Standard domino circuit
454.7
238.4
108.4
The proposed circuit
129.1
246.1
31.7