Table of Contents Author Guidelines Submit a Manuscript
Journal of Engineering
Volume 2013, Article ID 759761, 8 pages
http://dx.doi.org/10.1155/2013/759761
Research Article

A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique

1Faculty of Electronics and Telecommunications, University of Science, VNU-HCM, Ho Chi Minh City, Vietnam
2Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo 113-8656, Japan

Received 28 August 2012; Revised 3 December 2012; Accepted 11 December 2012

Academic Editor: Jan Van der Spiegel

Copyright © 2013 Trong-Tu Bui and Tadashi Shibata. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. V. A. Pedroni, “Compact hamming-comparator-based rank order filter for digital VLSI and FPGA implementations,” in Proceedings of the 2004 International Symposium on Circuits and Systems (ISCAS '04), pp. II585–II588, Vancouver, Canada, May 2004. View at Scopus
  2. L. R. Dung and M. C. Lin, “A maskable memory architecture for rank-order filtering,” IEEE Transactions on Consumer Electronics, vol. 50, no. 2, pp. 558–564, 2004. View at Publisher · View at Google Scholar · View at Scopus
  3. H. Yamasaki and T. Shibata, “A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits,” in Proceedings of the 31st European Solid-State Circuits Conference (ESSCIRC '05), pp. 125–128, Grenoble, France, September 2005. View at Publisher · View at Google Scholar · View at Scopus
  4. J. Ramírez-Angulo, C. Lackey, and A. Díaz-Sanchez, “Compact continuous-time analog rank-order filter implementation in CMOS technology,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '02), pp. V/65–V/68, Scottsdale, Ariz, USA, May 2002. View at Scopus
  5. J. Poikonen and A. Paasio, “A ranked order filter implementation for parallel analog processing,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 5, pp. 974–987, 2004. View at Publisher · View at Google Scholar · View at Scopus
  6. R. G. Carvajal, J. Ramírez-Angulo, G. O. Ducoudray, and A. J. López-Martín, “High-speed high-precision CMOS analog rank order filter with O(n) complexity,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1238–1248, 2005. View at Publisher · View at Google Scholar · View at Scopus
  7. L. T. Nguyen, K. Ito, and T. Shibata, “Compact and power-efficient implementation of rank-order filters using time-domain digital computation technique,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2807–2811, 2008. View at Publisher · View at Google Scholar · View at Scopus
  8. T. Shibata and T. Ohmi, “A functional MOS transistor featuring gate-level weighted sum and threshold operations,” IEEE Transactions on Electron Devices, vol. 39, no. 3, pp. 1444–1455, 1992. View at Publisher · View at Google Scholar
  9. D. K. Jeong, G. Borriello, D. A. Hodges, and R. H. Katz, “Design of PLL-based clock generation circuits,” IEEE Journal of Solid-State Circuits, vol. 22, no. 2, pp. 255–261, 1987. View at Google Scholar · View at Scopus
  10. S. Park, Y. Palaskas, and M. P. Flynn, “A 4-GS/s 4-bit flash ADC in 0.18 μn CMOS,” IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1865–1872, 2007. View at Publisher · View at Google Scholar · View at Scopus