A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box

Table 8

Comparisons with other small AES processors.

Design and FPGA (device)	CISA AES; ENC/DEC; (von-Neumann); Spartan-III (XC3S50-4)	Good and Benaissa [27]; AES ASIP; Spartan-II (XC2S15-6)	Good and Benaissa [27]; PicoBlaze; Spartan-II (XC2S15-6)	Gaj [28]; Spartan-II (XC2S30-6)	Rouvroy et al. [17]; Spartan-III (XC3S50-4)	Zhang and Parhi [2]; Virtex-E (XCV1000𝑒−8)
Encryption algorithm	AES	AES	AES	AES	AES	AES
Max. clock freq. (MHz)	20	72.3	90	60	71	168.4
Data-path bits	12	8	8	32	32	128
No. of slices of flip-flop utilized	110	122	119	222	163	11022
No. of block RAMs used	4	2	2	3	3	0
Block RAM size (kbits)	4	4	4	4	18	—
Bits of block RAM used	49152	4480	10666	9600	34176	0
Equiv. slices for memory	126	140	333	300	1068	0
Total equiv. slices (Est.)	236	262	452	522	1231	11022
Max throughput (Mbps)	—	—	—	166	208	21556
Avg. throughput (Mbps); Average encryption-decryption including key expansion	17.78	2.18	0.71	69	87	21556
Performance, typical throughput per slice (kbps/slice)	75.33	8.3	1.6	132	70	1956
Summary	Smallest	Very small	Software based	Best performance (throughput/slice)	Fastest	Loop unrolled