Research Article
Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style
Table 3
Performance comparison of the existing DyCML and the proposed H-DyCML 2-input XOR gate.
| Parameter | Style | DyCML | H-DyCML (Technique 1) |
H-DyCML (Technique 2) | H-DyCML (Technique 3) | PMOS | NMOS |
| Technology node 180 nm |
| Delay (ps) | 237.93 | 160.63 | 160.00 | 171.31 | 158.33 | Power (µW) | 29.28 | 14.84 | 14.84 | 13.23 | 15.20 | PDP (fJ) | 6.96 | 2.37 | 2.37 | 2.26 | 2.4 |
| Technology node 90 nm |
| Delay (ps) | 201 | 143 | 140 | 145 | 147 | Power (µW) | 24 | 14.8 | 14.8 | 14.91 | 13 | PDP (fJ) | 4.84 | 2.11 | 2.07 | 2.16 | 1.91 |
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