Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

Table 5

Performance comparison of the existing DyCML and the proposed H-DyCML 3-input XOR gate with single level of source-coupled transistors in the PDN.

Parameter	Style
	DyCML	H-DyCML (Technique 1)	H-DyCML (Technique 2)		H-DyCML (Technique 3)
			PMOS	NMOS
Technology node 180 nm
Delay (ps)	326.39	166	170	187	193
Power (µW)	26.54	18	17.5	19	17.6
PDP (fJ)	8.66	2.9	2.9	3.5	3.3
Technology node 90 nm
Delay (ps)	226	125	141	176	187
Power (µW)	23	16.2	16.8	18.4	16.7
PDP (fJ)	5.2	2.0	2.3	3.2	3.1