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Research Letters in Communications
Volume 2008, Article ID 435756, 5 pages
Research Letter

FPGA Implementation of Block Parallel DF-MPIC Detectors for DS-CDMA Systems in Frequency-Nonselective Channels

Department of Electrical and Computer Engineering, University of Quebec at Trois-Rivières, Trois-Rivières, Qc, Canada G9A 5H7

Received 19 August 2008; Accepted 9 October 2008

Academic Editor: Ibrahim Develi

Copyright © 2008 Adel Omar Dahmane and Lotfi Mejri. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Multistage parallel interference cancellation- (MPIC-) based detectors allow to mitigate multiple-access interference in direct-sequence code-division multiple-access (DS-CDMA) systems. They are considered serious candidates for practical implementation showing a good tradeoff between performance and complexity. Better performance is obtained when decision feedback (DF) is employed. Although MPIC and DF-MPIC have the same arithmetic complexity, DF-MPIC needs much more FPGA resources when compared to MPIC without decision feedback. In this letter, FPGA implementation of block parallel DF-MPIC (BP-DF-MPIC) is proposed allowing better tradeoff between performance and FPGA area occupancy. To reach an uncoded bit-error rate of 1 0 3 , BP-DF-MPIC shows a 1.5 dB improvement over the MPIC without decision feedback with only 8% increase in FPGA resources compared to 69% for DF-MPIC.