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Research Letters in Electronics
Volume 2009, Article ID 480740, 5 pages
Research Letter

Token-Aware Completion Functions for Elastic Processor Verification

Department of Electrical & Computer Engineering, North Dakota State University, Fargo, ND 58105, USA

Received 2 June 2009; Accepted 31 July 2009

Academic Editor: Massimo Poncino

Copyright © 2009 Sudarshan K. Srinivasan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA) specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.