Journal of Electrical and Computer Engineering / 2009 / Article / Fig 2

Research Letter

Token-Aware Completion Functions for Elastic Processor Verification

Figure 2

Network of elastic controllers for the elastic 5-stage DLX processor shown in Figure 1. The J and F blocks denote the join and fork circuits. Valid is used to indicate valid data in the datapath. Stop is used to indicate that EB cannot accept data at this time.

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