Review Article  Open Access
Two Integrator Loop Filters: Generation Using NAM Expansion and Review
Abstract
Systematic synthesis method to generate a family of two integrator loop filters based on nodal admittance matrix (NAM) expansion is given. Eight equivalent circuits are obtained; six of them are new. Each of the generated circuits uses two grounded capacitors and employs two current conveyors (CCII) or two inverting current conveyors (ICCII) or a combination of both. The NAM expansion is also used to generate eight equivalent grounded passive elements two integrator loop filters using differential voltage current conveyor (DVCC); six of them are new. Changing the input port of excitation, two new families of eight unity gain lowpass filter circuits each using two CCII or ICCII or combination of both or two DVCC are obtained.
1. Introduction
Recently, a symbolic framework for systematic synthesis of linear active circuits based on nodal admittance matrix (NAM) expansion was presented in [1, 2]. The matrix expansion process begins by introducing blank rows and columns, representing new internal nodes, in the admittance matrix. Then, nullators and norators are used to move the resulting admittance matrix elements to their final locations, properly describing either floating or grounded passive elements. Thus, the final NAM is obtained including finite elements representing passive circuit components.
In this framework, nullators and norators [3] that ideally describe active elements in the circuit are used. The nullator and norator are pathological elements that possess ideal characteristics and are specified according to the constraints they impose on their terminal voltages and currents. For the nullator , while the norator imposes no constraints on its voltage and current. A nullatornorator pair constitutes a universal active twoport network element called the nullor [3], and hence, nullator and norator are also called nullor elements.
Additional pathological elements called mirror elements were introduced in [4, 5] to describe the voltage and current reversing actions. The voltage mirror (VM) is a lossless twoport network element used to represent an ideal voltage reversing action and is described by
The magnitude of the DC gain of the lowpass filter is unity.
5. Two Integrator Loop Filters Using DVCC
5.1. Generation Using Brackets
The NAM expansion introduced in Sections 3 and 4 can also be used to generate high input impedance twostage two integrator loop filter circuits using the DVCC as the basic building block. The single output differential difference current conveyor (DDCC) has been introduced in [16]. The same circuit defined as the DVCC with a balanced output has also been independently introduced in [17].
The DVCC with a single output is a fourport building block defined by [16, 17]
It is seen that the DVCC includes CCII and ICCII as special cases. The DVCC with a single output is defined by [17]
It is seen that the DVCC includes CCII and ICCII as special cases.
The typeA DVCCbased two integrator loop filter circuits are generated from Figure 2 by following the pathological elements between nodes 2 and 3 to determine the input of DVCC1 and then insert input source at the other input of DVCC1. If the pathological element between nodes 2 and 3 is a nullator, then the feedback to DVCC1 will be to and input source is applied to which will represent the additional node in this case. If the pathological element between nodes 2 and 3 is a VM, then the feedback to DVCC1 will be to and input source is applied to Y_{1}.
The DVCC2 uses one input which is identified from the pathological element between nodes 1 and 4, if it is a nullator, then will be input node of DVCC2 and will be grounded; on the otherhand if it is a VM, then will be input node of DVCC2 and will be grounded.
The Z polarities will be determined from the pathological elements between nodes 1, 3 and between nodes 2 and 4 as in the case of CCII and ICCII.
For example, in the A1 circuit a CM is connected between nodes 1 and 3 which implies that polarity for the DVCC1, and a norator is connected between nodes 2 and 4 which implies that polarity for DVCC2.
Figure 5 represents the four typeA two DVCCbased two integrator loop filter circuits, and the bandpass and lowpass polarities are given in Table 2. It should be noted that the second stage in each of the four circuits is used as a CCII or as ICCII.
(a) Circuit A1 using two DVCC
(b) Circuit A2 using two DVCC
(c) Circuit A3 using two DVCC
(d) Circuit A4 using two DVCC
Figure 6 represents the four typeB two DVCCbased two integrator loop filter circuits, and the bandpass and lowpass polarities are given in Table 2.
(a) Circuit B1 using two DVCC
(b) Circuit B2 using two DVC
(c) Circuit B3 using two DVCC
(d) Circuit B4 using two DVCC
It should be noted that the second stage in each of the four circuits is used as a CCII or as ICCII.
The transfer functions for each of the eight DVCCbased two integrator loop filter circuits are the same as given by (17) to (20).
It should be noted that the block diagram representing the circuits of Figure 5 is the same as that of Figure 1 with upper integrator signs but with a negative sign of the summer input connected to . Similarly the block diagram representing the circuits of Figure 6 is the same as that of Figure 1 with the lower integrator signs but with a negative sign of the summer input connected to .
5.2. Generation Using Brackets and Infinity Parameters
The NAM expansion can also be carried out using both the brackets method and the infinity parameters.
The infinity parameter representation of the DVCC is given by [18]
The infinity parameter representation of the DVCC is given by [18]
The brackets are used to realize the second stage of the circuit, and the infinity parameters are used next to realize the first stage.
As an example consider the generation of the circuit of Figure 5(a). Starting from (6), add two blank rows and columns and then connect a nullator between nodes 1 and 4 and a norator between nodes 2 and 4 to move to the diagonal position 4, 4 as follows:
(25)
The nullator and norator added to move are realizable by a CCII which is realized by the DVCC with port connected to and with port connected to ground. Next is connected to port 1 and the capacitors to node 1 and are connected to nodes 1 and 2, respectively.
To realize a highinput impedance circuit there must be a row with a zero current; adding a fifth blank row and column results in the following expanded NAM:
(26)
The infinity parameters moves in a twostep move to the diagonal 3, 3 position as follows:
(27)
The infinity parameters realizes the first stage DVCC with its as the highinput impedance node 5, as node 2 and as node 3 connected to to ground as shown in Figure 5(a).
As a second example consider the generation of the circuit of Figure 5(c).
The NAM can also be expanded as follows:
(28)
The above equation is realized as shown in Figure 5(c) with the first stage as a DVCC with its as the highinput impedance node 5 and connected to input, as node 2, and as node 3 connected to to ground; the second stage is the same as in Figure 5(a).
The typeB DVCCbased two integrator loop filter circuits can also be generated following the same rules mentioned above.
6. Generation of New Lowpass Filters
A new family of lowpass filters can be generated from the generalized circuit of Figure 3 by injecting the input voltage at node and grounding node . The generalized lowpass filter circuit is shown in Figure 7(a) with the same transfer function as given by (18). The magnitude of the DC gain is unity and the polarity is given in Table 3. Eight new alternative realizations that belong to Figure 7(a) according to the conveyors used are given in Table 3. The generalized block diagram of this family of lowpass filters is obtained from Figure 1 by interchanging the two integrator positions [12, 19]. It is worth noting that the circuit numbers three and six have a floating property.

(a) A generalized two conveyors lowpass filter
(b) Lowpass filter obtained from circuit A1 in Figure 5(a)
Similarly eight new DVCCbased lowpass filter circuits can be generated from Figures 5 and 6 by changing the input port of excitation. Figure 7(b) represents the new noninverting lowpass filter circuit generated from Figure 5(a). similarly the other seven lowpass filter circuits can be obtained.
7. Conclusions
The NAM expansion method using nullor elements and pathological mirrors is used to generate eight grounded capacitor conveyorbased two integrator loop filter circuits. Additional eight grounded passive elements DVCCbased two integrator loop filter circuits are given; six of them are new. The CCII circuits A1 and B1 have been reported before in [14]. It is worth noting that circuits A3 and B2 have a floating property as shown in Table 1.
Additional eight grounded passive elements DVCCbased circuits are given; six of them are new. It is worth noting that circuits A3 and B2 have a floating property as shown in Table 2.
It is worth noting that all the reported circuits whether employing CCII and ICCII combinations or using two DVCC can be compensated by subtracting the values of the parasitic resistances and from the design values of and respectively. Similarly the parasitic capacitances can be compensated by subtracting the values of and from the design values of and , respectively.
A similar circuit to B1 using two CCII with different port excitations was given in [20]. Other realizations of two integrator loop filter circuits using ICCII were given in [21]. The importance of the VMCM pathological elements [22] in the generation of the six new two integrator loop filter circuits using CCII or ICCII or combination of both or two DVCC is demonstrated in this review paper.
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Copyright
Copyright © 2010 Ahmed M. Soliman. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.