Comparison of Memory Assignment Schemes for Switch Architectures with Shareable Parallel Memory Modules

Table 1

Worst-case scenario for number of memory-cycles required per switch cycle for packets’ READ or WRITE memory operations in SMB and SW switches, respectively.

	Load = 80%			Load = 100%
Number of Memory Cycles	SW New Scheme	SW Previous Scheme	SMB Scheme	SW New Scheme	SW Previous Scheme	SMB Scheme
1 Cycle	100%	99.7046%	71.9705%	100%	89.4748%	64.3640%
2 Cycles	0%	0.2954%	24.6341%	0%	10.5016%	28.9760%
3 Cycles	0%	0%	3.1929%	0%	0.0237%	5.8846%
4 Cycles	0%	0%	0.1957%	0%	0%	0.7160%
5 Cycles	0%	0%	0.0066%	0%	0%	0.0561%
6 Cycles	0%	0%	0.0001%	0%	0%	0.0032%
7 Cycles	0%	0%	0%	0%	0%	0.0001%