Journal of Electrical and Computer Engineering

Research Article

New RTD-Based General Threshold Gate Topologies and Application to Three-Input XOR Logic Gates

Figure 1

(a) The proposed GTG-2 three-input XOR. RTD areas are 𝑤 1 𝐴 , 𝑤 3 𝐴 , 𝑤 4 𝐴 , 𝑤 5 𝐴 = 2 𝜇 m 2 , and 𝑤 2 𝐴 = 3 𝜇 m 2 . After eliminating the dotted RTD (GTG-4) other RTD areas are: 𝑤 1 𝐴 , 𝑤 4 𝐴 , 𝑤 5 𝐴 = 2 𝜇 m 2 , 𝑤 2 𝐴 = 3 𝜇 m 2 , and 𝑤 3 𝐴 = infinity (i.e., RTD replaced with a short circuit). (b) The proposed GTG-3 three-input XOR. RTD areas are 𝑤 3 𝐴 , 𝑤 2 𝐴 = 2 𝜇 m 2 , and 𝑤 1 𝐴 = 3 𝜇 m 2 and after eliminating the dotted RTD (GTG-5) other RTD areas are 𝑤 3 𝐴 = infinity (i.e., RTD replaced with a short circuit), 𝑊 2 𝐴 = 2 𝜇 m 2 , and 𝑊 1 𝐴 = 3 𝜇 m 2 . In this figure the transistors widths are shown as well. The transistors in the same row have the same size ( 𝜇 m) and parenthesized numbers show the values for GTG-4 and GTG-5 (after replacing the RTDs with short circuits). For modeling the transistors, a 130 nm HSPICE transistor model is used.
463925.fig.001a
(a)
463925.fig.001b
(b)