New RTD-Based General Threshold Gate Topologies and Application to Three-Input XOR Logic Gates

Figure 2

The simulation results for proposed XOR gate circuits. (a) The clock (𝑉_bias=0.8). (b), (c), and (d) are the three input waveform which are 𝑉_HIGH=0.75 V and 𝑉_LOW=0. (e) The output result for the proposed GTG-2 XOR. (f) The output result for the proposed GTG-3 XOR. (g) The output result for the proposed GTG-4 (modified GTG-2) XOR. (h) The output result for the proposed GTG-5 (modified GTG-3) XOR.

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