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Journal of Electrical and Computer Engineering
Volume 2010, Article ID 515021, 7 pages
http://dx.doi.org/10.1155/2010/515021
Research Article

Optimization Techniques for Verification of Out-of-Order Execution Machines

Department of Electrical & Computer Engineering, North Dakota State University, Fargo, ND 58105, USA

Received 22 March 2010; Accepted 17 August 2010

Academic Editor: Dhiraj K. Pradhan

Copyright © 2010 Sudarshan K. Srinivasan. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We develop two optimization techniques, flush-machine and collapsed flushing, to improve the efficiency of automatic refinement-abased verification of out-of-order (ooo) processor models. Refinement is a notion of equivalence that can be used to check that an ooo processor correctly implements all behaviors of its instruction set architecture (ISA), including deadlock detection. The optimization techniques work by reducing the computational complexity of the refinement map, a function central to refinement proofs that maps ooo processor model states to ISA states. This has a direct impact on the efficiency of verification, which is studied using 23 ooo processor models. Flush-machine, is a novel optimization technique. Collapsed flushing has been employed previously in the context of in-order processors. We show how to apply collapsed flushing for ooo processor models. Using both the optimizations together, we can handle 9 ooo models that could not be verified using standard flushing. Also, the optimizations provided a speed up of 23.29 over standard flushing.