Multi-FPGA Partitioning Method Based on Topological Levelization

Table 1

Partitioning results for the Wildforce-XL, the SLAAC, the MSP boards.

Partitioning results for the Wildforce-XL platform
Netlists	#CLBs	#RAMs	#Nodes	#Nets	RPL algorithm		RP algorithm		HP algorithm
					#Partitions	Time(s)	#Partitions	Time(s)	#Partitions	Time(s)
ATR	4885	14	101	234	20	2	23	9	Not feasible	—
R29	519	7	29	28	9	<1	Not feasible	—	Not feasible	—
R300	7845	11	301	311	21	3	23	26	25	4
R600	17640	9	702	714	23	21	24	138	29	34
R1000	24533	23	1005	1041	55	101	58	236	58	184
R1300	33120	25	1303	1243	64	225	66	501	72	424
R1500	41453	34	1502	1497	88	371	91	863	Not feasible	—
Partitioning results for the SLAAC-1V platform
ATR	4885	14	101	234	4	<1	5	2	5	1
R29	519	7	29	28	2	<1	2	<1	2	<1
R300	7845	11	301	311	4	<1	4	11	4	2
R600	17640	9	702	714	3	11	3	89	3	19
R1000	24533	23	1005	1041	8	63	8	174	8	131
R1300	33120	25	1303	1243	8	127	8	379	8	289
R1500	41453	34	1502	1497	11	193	11	434	11	351
Partitioning results for the MSP platform
ATR	4885	14	101	234	12	1	14	7	14	1
R29	519	7	29	28	6	<1	6	<1	6	<1
R300	7845	11	301	311	10	3	10	21	10	3
R600	17640	9	702	714	7	21	7	113	7	29
R1000	24533	23	1005	1041	21	76	21	222	22	172
R1300	33120	25	1303	1243	23	181	24	471	24	401
R1500	41453	34	1502	1497	32	273	33	604	34	503