Research Article
Semidigital PLL Design for Low-Cost Low-Power Clock Generation
Table 2
Measured performance summary [
14].
| | Process | 0.18 μm CMOS | | Supply Voltage | 1.8 V for analog, 1.5 V for digital | | Power consumption | Total: 16.8 mW
(Analog: 11.9 mW, Digital: 4.9 mW) | | Occupied area | Active area: ~0.6 mm2 (LPF < 0.04 mm2) | | VCO tuning range | 790–925 MHz | | Reference clock | 30 MHz | | Reference spur | <−52 dBc | | Phase noise | <−81 dBc/Hz | | Integrated RMS noise | 100 kHz~100 MHz: 12.6°rms
10 MHz~100 MHz: 1.1°rms |
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