Research Article
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
Table 2
PFSCL Tristate gates based on switch transistor technique.
| Gate | (ns) | Power dissipation (W) | Power delay product (fJ) |
| Inverter | 0.145 | 16.2 | 2.349 | NAND | 0.575 | 16.2 | 9.315 | NOR | 0.395 | 16.2 | 6.399 |
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