Research Article
New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic
Table 3
PFSCL Tristate gates based on sleep transistor technique.
| | Gate | (ns) | Power Dissipation (W) | Power delay product (fJ) |
| | Inverter | 0.105 | 8.1 | 0.85 | | NAND | 0.148 | 8.1 | 1.199 | | NOR | 0.107 | 8.1 | 0.867 |
|
|
