VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="936712.fig.0014a" src="https://static.hindawi.com/articles/jece/volume-2011/936712/figures/936712.fig.0014a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Half periods</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="936712.fig.0014b" src="https://static.hindawi.com/articles/jece/volume-2011/936712/figures/936712.fig.0014b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Clock frequency</td></tr></table></td></tr></table>

<table>Single clock evaluation of a running standard node cluster.</table>

Journal of Electrical and Computer Engineering

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Figure 14

Figure 14: VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation 