VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

Table 2

Cluster of 8 standard nodes: voltage scaling.

Core voltage in (V)	Avg. frequency in (MHz)	Current ASIC U6 in (mA)	Current all in (mA)
1.3	38	11.7	100
1.4	43	15.1	126
1.5	47	17.6	150
1.6	50	20.6	178
1.7	52	23.8	204
1.8	54	27.2	233