Journal of Electrical and Computer Engineering / 2012 / Article / Tab 5

Research Article

A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level

Table 5

Maximal computational complexity and utilization of the processing resources observed for the two architectures considered.

Architecture IArchitecture II
𝑃 1 𝑃 2 𝑃 3
Maximal computational complexity (GOPS)Resource usage (%)Maximal computational complexity (GOPS)Resource usage (%)Maximal computational complexity (GOPS)Resource usage (%)

OFDMDemodulator1,61220β€”β€”0,322100
ChannelEstimator0,40648β€”β€”0,24480
Equalizer0,15112β€”β€”0,0380
TurboDecoderβ€”β€”221,778177,4910
Application1,61280221,778177,812β€”

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