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<table>Circuit resulting after the algorithm’s steps.</table>

Journal of Electrical and Computer Engineering

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Figure 9

Figure 9: An Optimization Mechanism Intended for Static Power Reduction Using Dual-<svg style="vertical-align:-4.62607pt;width:25.975px;" id="M1" height="20.525" version="1.1" viewBox="0 0 25.975 20.525" width="25.975"  xmlns="http://www.w3.org/2000/svg">
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Journal of Electrical and Computer Engineering

An Optimization Mechanism Intended for Static Power Reduction Using Dual- 𝑉 t h Technique

Figure 9

An Optimization Mechanism Intended for Static Power Reduction Using Dual-Technique