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Journal of Electrical and Computer Engineering
Volume 2012, Article ID 614259, 14 pages
Research Article

VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

School of Electronic and Electrical Engineering, University of Leeds, Leeds LS2 9JT, UK

Received 15 July 2011; Revised 17 February 2012; Accepted 4 April 2012

Academic Editor: Zhiyuan Yan

Copyright © 2012 Georgios Passas and Steven Freear. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.