Low-Jitter 0.1-to-5.8 GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Table 3

Clock synthesizer performance summary and comparison.

Ref.	VCO output frequency (GHz)	RMS jitter (psrms), integration band	Active area (mm^2)	Power consumption, nominal supply	Process technology
[2]	Ring VCO: 1.0 to 8.5; LC-VCO: 8.3 to 11.1	0.99 (1 MHz to 1.25 GHz); 0.55 (1 MHz to 1.25 GHz)	0.277	Ring VCO: 70 mW; LC-VCO: 60 mW; 2.5 V	45 nm; SOI-CMOS
[3]	0.2 to 4	1.5; (integration band not reported)	not reported	15 mW; Analog: 1.8 V; Digital: 1 V	65 nm; CMOS
[7]	2.29 to 2.75	0.97; (10 kHz to 10 MHz)	5.12; (entire core)	120 mW; Analog: 3 V,; Digital: 2 V	0.35 𝜇m; CMOS
[8]	5.7 to 6.8	0.56; (integration band not reported)	0.43	25 mW; Not reported	0.13 𝜇m; CMOS
[9]	6.33 to 10.56	1.3; (integration band not reported)	3.5; (entire core)	88.5 mW; 1.5 V	0.18 𝜇m; CMOS
This work	3.6 to 5.8; (~0 to 5.8 Gb/s baud rate using dividers)	0.45 (12 kHz to 20 MHz); 0.47 (2.55 MHz to 2.125 GHz); 0.54 (1 kHz to 40 MHz)	0.39	20 mW; 1 V	65 nm; CMOS