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Journal of Electrical and Computer Engineering
Volume 2013, Article ID 454392, 13 pages
Research Article

Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Department of Electrical and Computer Engineering, Royal Military College of Canada, P.O. Box 17000, Station Forces, Kingston ON, Canada K7K 7B4

Received 14 May 2013; Revised 12 August 2013; Accepted 26 August 2013

Academic Editor: Mohamad Sawan

Copyright © 2013 Farid Moshgelani et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14-transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25 nm FinFET technology using the University of Florida UFDG model.