Journal of Electrical and Computer Engineering

Research Article

Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Figure 4

(a) The IG/LP mode of the symmetric mirror full adder, (b) the IG/LP mode of the asymmetric mirror full adder.
454392.fig.004a
(a)
454392.fig.004b
(b)