Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

<table>(a) Optimal configuration of the symmetric 14T full adder circuit, (b) optimal configuration of the asymmetric 14T full adder circuit.</table>

Journal of Electrical and Computer Engineering

Figure 5: Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs 