Research Article
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs
Table 12
Comparison between different scenarios for 3 : 2 symmetric FinFET compressor.
| | Scenario | (pA) | (ps) | Static power * delay (zJ) | Number of transistors |
| | 1 | 76.63 | 31.53 | 2.89 | 30 | | 2 | 182.51 | 26.99 | 5.91 | 22 | | 3 | 137.68 | 23.47 | 3.87 | 18 |
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