Research Article

Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Table 6

Results for the complete mirror full adder.

IG/LP modeSymmetric 
= −0.2 V
Asymmetric 
= 0 V

(pA)49.856.24
(ps)37.0539.52
Static power * delay (zJ)2.210.30