Research Article
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs
Table 7
Results for the 14T full adder.
| Optimal-mode | Symmetric = −0.2 V | Asymmetric = 0 V |
| (pA) | 38.47 | 5.85 | (ps) | 24.03 | 28.52 | Static Power * delay (zJ) | 1.10 | 0.20 |
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