Research Article
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs
Table 8
Results for the TG full adder.
| Optimal mode | Symmetric = −0.2 V | Asymmetric = 0 V |
| (pA) | 74.79 | 11.56 | (ps) | 26.56 | 24.79 | Static power * delay (zJ) | 2.38 | 0.34 |
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