Journal of Electrical and Computer Engineering / 2013 / Article / Fig 1

Research Article

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Figure 1

Example of a 3-tap DFFE ( ) with . (a) Note that the latency between the input signal and the decision is . (b) The red dashed line denotes the critical path (see Section 4.4).

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