Journal of Electrical and Computer Engineering / 2013 / Article / Fig 7

Research Article

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Figure 7

Number of adders, registers, and 2-to-1 multiplexers versus the number of feedback taps , for the parallel DFFE with and DFE architectures proposed in [4, 7, 9, 10]. Parallelization factor: . Modulation format: 2-PAM.

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